fen2.rpt

用vhdl写的

        | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | A B |     Logic cells that feed LAB 'B':

Pin
4    -> * * * * * * * * | - * | <-- CS
25   -> * - - - - - - - | - * | <-- IN10
39   -> - * - - - - - - | - * | <-- IN11
38   -> - - * - - - - - | - * | <-- IN12
29   -> - - - * - - - - | - * | <-- IN13
32   -> - - - - * - - - | - * | <-- IN14
5    -> - - - - - * - - | - * | <-- IN15
6    -> - - - - - - * - | - * | <-- IN16
7    -> - - - - - - - * | - * | <-- IN17
8    -> * - - - - - - - | - * | <-- IN20
9    -> - * - - - - - - | - * | <-- IN21
11   -> - - * - - - - - | - * | <-- IN22
12   -> - - - * - - - - | - * | <-- IN23
13   -> - - - - * - - - | - * | <-- IN24
14   -> - - - - - * - - | - * | <-- IN25
16   -> - - - - - - * - | - * | <-- IN26
17   -> - - - - - - - * | - * | <-- IN27
18   -> * - - - - - - - | - * | <-- IN30
19   -> - * - - - - - - | - * | <-- IN31
20   -> - - * - - - - - | - * | <-- IN32
21   -> - - - * - - - - | - * | <-- IN33
43   -> - - - - * - - - | - * | <-- IN34
44   -> - - - - - * - - | - * | <-- IN35
37   -> - - - - - - * - | - * | <-- IN36
36   -> - - - - - - - * | - * | <-- IN37
27   -> * * * * * * * * | - * | <-- SW_B


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                              d:\xiaoning\fen2.rpt
fen2

** EQUATIONS **

CS       : INPUT;
IN10     : INPUT;
IN11     : INPUT;
IN12     : INPUT;
IN13     : INPUT;
IN14     : INPUT;
IN15     : INPUT;
IN16     : INPUT;
IN17     : INPUT;
IN20     : INPUT;
IN21     : INPUT;
IN22     : INPUT;
IN23     : INPUT;
IN24     : INPUT;
IN25     : INPUT;
IN26     : INPUT;
IN27     : INPUT;
IN30     : INPUT;
IN31     : INPUT;
IN32     : INPUT;
IN33     : INPUT;
IN34     : INPUT;
IN35     : INPUT;
IN36     : INPUT;
IN37     : INPUT;
SW_B     : INPUT;

-- Node name is 'EW0' 
-- Equation name is 'EW0', location is LC023, type is output.
 EW0     = LCELL( _EQ001 $  GND);
  _EQ001 =  CS &  IN10 &  SW_B
         # !CS &  IN30 &  SW_B
         #  IN20 & !SW_B;

-- Node name is 'EW1' 
-- Equation name is 'EW1', location is LC024, type is output.
 EW1     = LCELL( _EQ002 $  GND);
  _EQ002 =  CS &  IN11 &  SW_B
         # !CS &  IN31 &  SW_B
         #  IN21 & !SW_B;

-- Node name is 'EW2' 
-- Equation name is 'EW2', location is LC026, type is output.
 EW2     = LCELL( _EQ003 $  GND);
  _EQ003 =  CS &  IN12 &  SW_B
         # !CS &  IN32 &  SW_B
         #  IN22 & !SW_B;

-- Node name is 'EW3' 
-- Equation name is 'EW3', location is LC028, type is output.
 EW3     = LCELL( _EQ004 $  GND);
  _EQ004 =  CS &  IN13 &  SW_B
         # !CS &  IN33 &  SW_B
         #  IN23 & !SW_B;

-- Node name is 'EW4' 
-- Equation name is 'EW4', location is LC030, type is output.
 EW4     = LCELL( _EQ005 $  GND);
  _EQ005 =  CS &  IN14 &  SW_B
         # !CS &  IN34 &  SW_B
         #  IN24 & !SW_B;

-- Node name is 'EW5' 
-- Equation name is 'EW5', location is LC032, type is output.
 EW5     = LCELL( _EQ006 $  GND);
  _EQ006 =  CS &  IN15 &  SW_B
         # !CS &  IN35 &  SW_B
         #  IN25 & !SW_B;

-- Node name is 'EW6' 
-- Equation name is 'EW6', location is LC017, type is output.
 EW6     = LCELL( _EQ007 $  GND);
  _EQ007 =  CS &  IN16 &  SW_B
         # !CS &  IN36 &  SW_B
         #  IN26 & !SW_B;

-- Node name is 'EW7' 
-- Equation name is 'EW7', location is LC018, type is output.
 EW7     = LCELL( _EQ008 $  GND);
  _EQ008 =  CS &  IN17 &  SW_B
         # !CS &  IN37 &  SW_B
         #  IN27 & !SW_B;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                       d:\xiaoning\fen2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,452K