📄 fen2.rpt
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Project Information d:\xiaoning\fen2.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 12/01/2004 19:11:32
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
FEN2
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
fen2 EPM7032LC44-6 26 8 0 8 0 25 %
User Pins: 26 8 0
Device-Specific Information: d:\xiaoning\fen2.rpt
fen2
***** Logic for device 'fen2' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
Device-Specific Information: d:\xiaoning\fen2.rpt
fen2
** ERROR SUMMARY **
Info: Chip 'fen2' in device 'EPM7032LC44-6' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
I I I I
N N V G G N N G E E
1 1 C C N N 3 3 N W W
6 5 S C D D 5 4 D 6 7
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
IN17 | 7 39 | IN11
IN20 | 8 38 | IN12
IN21 | 9 37 | IN36
GND | 10 36 | IN37
IN22 | 11 35 | VCC
IN23 | 12 EPM7032LC44-6 34 | EW0
IN24 | 13 33 | EW1
IN25 | 14 32 | IN14
VCC | 15 31 | EW2
IN26 | 16 30 | GND
IN27 | 17 29 | IN13
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
I I I I G V E I E S E
N N N N N C W N W W W
3 3 3 3 D C 5 1 4 _ 3
0 1 2 3 0 B
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\xiaoning\fen2.rpt
fen2
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 16/16(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 8/16( 50%) 16/16(100%) 0/16( 0%) 26/36( 72%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 32/32 (100%)
Total logic cells used: 8/32 ( 25%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 8/32 ( 25%)
Total shareable expanders not available (n/a): 0/32 ( 0%)
Average fan-in: 5.00
Total fan-in: 40
Total input pins required: 26
Total output pins required: 8
Total bidirectional pins required: 0
Total logic cells required: 8
Total flipflops required: 0
Total product terms required: 24
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: d:\xiaoning\fen2.rpt
fen2
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 (1) (A) INPUT 0 0 0 0 0 8 0 CS
25 (31) (B) INPUT 0 0 0 0 0 1 0 IN10
39 (19) (B) INPUT 0 0 0 0 0 1 0 IN11
38 (20) (B) INPUT 0 0 0 0 0 1 0 IN12
29 (27) (B) INPUT 0 0 0 0 0 1 0 IN13
32 (25) (B) INPUT 0 0 0 0 0 1 0 IN14
5 (2) (A) INPUT 0 0 0 0 0 1 0 IN15
6 (3) (A) INPUT 0 0 0 0 0 1 0 IN16
7 (4) (A) INPUT 0 0 0 0 0 1 0 IN17
8 (5) (A) INPUT 0 0 0 0 0 1 0 IN20
9 (6) (A) INPUT 0 0 0 0 0 1 0 IN21
11 (7) (A) INPUT 0 0 0 0 0 1 0 IN22
12 (8) (A) INPUT 0 0 0 0 0 1 0 IN23
13 (9) (A) INPUT 0 0 0 0 0 1 0 IN24
14 (10) (A) INPUT 0 0 0 0 0 1 0 IN25
16 (11) (A) INPUT 0 0 0 0 0 1 0 IN26
17 (12) (A) INPUT 0 0 0 0 0 1 0 IN27
18 (13) (A) INPUT 0 0 0 0 0 1 0 IN30
19 (14) (A) INPUT 0 0 0 0 0 1 0 IN31
20 (15) (A) INPUT 0 0 0 0 0 1 0 IN32
21 (16) (A) INPUT 0 0 0 0 0 1 0 IN33
43 - - INPUT 0 0 0 0 0 1 0 IN34
44 - - INPUT 0 0 0 0 0 1 0 IN35
37 (21) (B) INPUT 0 0 0 0 0 1 0 IN36
36 (22) (B) INPUT 0 0 0 0 0 1 0 IN37
27 (29) (B) INPUT 0 0 0 0 0 8 0 SW_B
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\xiaoning\fen2.rpt
fen2
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
34 23 B OUTPUT t 0 0 0 5 0 0 0 EW0
33 24 B OUTPUT t 0 0 0 5 0 0 0 EW1
31 26 B OUTPUT t 0 0 0 5 0 0 0 EW2
28 28 B OUTPUT t 0 0 0 5 0 0 0 EW3
26 30 B OUTPUT t 0 0 0 5 0 0 0 EW4
24 32 B OUTPUT t 0 0 0 5 0 0 0 EW5
41 17 B OUTPUT t 0 0 0 5 0 0 0 EW6
40 18 B OUTPUT t 0 0 0 5 0 0 0 EW7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\xiaoning\fen2.rpt
fen2
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------------- LC23 EW0
| +------------- LC24 EW1
| | +----------- LC26 EW2
| | | +--------- LC28 EW3
| | | | +------- LC30 EW4
| | | | | +----- LC32 EW5
| | | | | | +--- LC17 EW6
| | | | | | | +- LC18 EW7
| | | | | | | |
| | | | | | | | Other LABs fed by signals
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