sdr_test.hier_info

来自「sdram读写」· HIER_INFO 代码 · 共 1,777 行 · 第 1/5 页

address_b[4] => ram_block15a2.PORTBADDR4
address_b[4] => ram_block15a3.PORTBADDR4
address_b[4] => ram_block15a4.PORTBADDR4
address_b[4] => ram_block15a5.PORTBADDR4
address_b[4] => ram_block15a6.PORTBADDR4
address_b[4] => ram_block15a7.PORTBADDR4
address_b[4] => ram_block15a8.PORTBADDR4
address_b[4] => ram_block15a9.PORTBADDR4
address_b[4] => ram_block15a10.PORTBADDR4
address_b[4] => ram_block15a11.PORTBADDR4
address_b[4] => ram_block15a12.PORTBADDR4
address_b[4] => ram_block15a13.PORTBADDR4
address_b[4] => ram_block15a14.PORTBADDR4
address_b[4] => ram_block15a15.PORTBADDR4
address_b[5] => ram_block15a0.PORTBADDR5
address_b[5] => ram_block15a1.PORTBADDR5
address_b[5] => ram_block15a2.PORTBADDR5
address_b[5] => ram_block15a3.PORTBADDR5
address_b[5] => ram_block15a4.PORTBADDR5
address_b[5] => ram_block15a5.PORTBADDR5
address_b[5] => ram_block15a6.PORTBADDR5
address_b[5] => ram_block15a7.PORTBADDR5
address_b[5] => ram_block15a8.PORTBADDR5
address_b[5] => ram_block15a9.PORTBADDR5
address_b[5] => ram_block15a10.PORTBADDR5
address_b[5] => ram_block15a11.PORTBADDR5
address_b[5] => ram_block15a12.PORTBADDR5
address_b[5] => ram_block15a13.PORTBADDR5
address_b[5] => ram_block15a14.PORTBADDR5
address_b[5] => ram_block15a15.PORTBADDR5
address_b[6] => ram_block15a0.PORTBADDR6
address_b[6] => ram_block15a1.PORTBADDR6
address_b[6] => ram_block15a2.PORTBADDR6
address_b[6] => ram_block15a3.PORTBADDR6
address_b[6] => ram_block15a4.PORTBADDR6
address_b[6] => ram_block15a5.PORTBADDR6
address_b[6] => ram_block15a6.PORTBADDR6
address_b[6] => ram_block15a7.PORTBADDR6
address_b[6] => ram_block15a8.PORTBADDR6
address_b[6] => ram_block15a9.PORTBADDR6
address_b[6] => ram_block15a10.PORTBADDR6
address_b[6] => ram_block15a11.PORTBADDR6
address_b[6] => ram_block15a12.PORTBADDR6
address_b[6] => ram_block15a13.PORTBADDR6
address_b[6] => ram_block15a14.PORTBADDR6
address_b[6] => ram_block15a15.PORTBADDR6
address_b[7] => ram_block15a0.PORTBADDR7
address_b[7] => ram_block15a1.PORTBADDR7
address_b[7] => ram_block15a2.PORTBADDR7
address_b[7] => ram_block15a3.PORTBADDR7
address_b[7] => ram_block15a4.PORTBADDR7
address_b[7] => ram_block15a5.PORTBADDR7
address_b[7] => ram_block15a6.PORTBADDR7
address_b[7] => ram_block15a7.PORTBADDR7
address_b[7] => ram_block15a8.PORTBADDR7
address_b[7] => ram_block15a9.PORTBADDR7
address_b[7] => ram_block15a10.PORTBADDR7
address_b[7] => ram_block15a11.PORTBADDR7
address_b[7] => ram_block15a12.PORTBADDR7
address_b[7] => ram_block15a13.PORTBADDR7
address_b[7] => ram_block15a14.PORTBADDR7
address_b[7] => ram_block15a15.PORTBADDR7
address_b[8] => ram_block15a0.PORTBADDR8
address_b[8] => ram_block15a1.PORTBADDR8
address_b[8] => ram_block15a2.PORTBADDR8
address_b[8] => ram_block15a3.PORTBADDR8
address_b[8] => ram_block15a4.PORTBADDR8
address_b[8] => ram_block15a5.PORTBADDR8
address_b[8] => ram_block15a6.PORTBADDR8
address_b[8] => ram_block15a7.PORTBADDR8
address_b[8] => ram_block15a8.PORTBADDR8
address_b[8] => ram_block15a9.PORTBADDR8
address_b[8] => ram_block15a10.PORTBADDR8
address_b[8] => ram_block15a11.PORTBADDR8
address_b[8] => ram_block15a12.PORTBADDR8
address_b[8] => ram_block15a13.PORTBADDR8
address_b[8] => ram_block15a14.PORTBADDR8
address_b[8] => ram_block15a15.PORTBADDR8
addressstall_a => ram_block15a0.PORTAADDRSTALL
addressstall_a => ram_block15a1.PORTAADDRSTALL
addressstall_a => ram_block15a2.PORTAADDRSTALL
addressstall_a => ram_block15a3.PORTAADDRSTALL
addressstall_a => ram_block15a4.PORTAADDRSTALL
addressstall_a => ram_block15a5.PORTAADDRSTALL
addressstall_a => ram_block15a6.PORTAADDRSTALL
addressstall_a => ram_block15a7.PORTAADDRSTALL
addressstall_a => ram_block15a8.PORTAADDRSTALL
addressstall_a => ram_block15a9.PORTAADDRSTALL
addressstall_a => ram_block15a10.PORTAADDRSTALL
addressstall_a => ram_block15a11.PORTAADDRSTALL
addressstall_a => ram_block15a12.PORTAADDRSTALL
addressstall_a => ram_block15a13.PORTAADDRSTALL
addressstall_a => ram_block15a14.PORTAADDRSTALL
addressstall_a => ram_block15a15.PORTAADDRSTALL
clock0 => ram_block15a0.CLK0
clock0 => ram_block15a1.CLK0
clock0 => ram_block15a2.CLK0
clock0 => ram_block15a3.CLK0
clock0 => ram_block15a4.CLK0
clock0 => ram_block15a5.CLK0
clock0 => ram_block15a6.CLK0
clock0 => ram_block15a7.CLK0
clock0 => ram_block15a8.CLK0
clock0 => ram_block15a9.CLK0
clock0 => ram_block15a10.CLK0
clock0 => ram_block15a11.CLK0
clock0 => ram_block15a12.CLK0
clock0 => ram_block15a13.CLK0
clock0 => ram_block15a14.CLK0
clock0 => ram_block15a15.CLK0
clock1 => ram_block15a0.CLK1
clock1 => ram_block15a1.CLK1
clock1 => ram_block15a2.CLK1
clock1 => ram_block15a3.CLK1
clock1 => ram_block15a4.CLK1
clock1 => ram_block15a5.CLK1
clock1 => ram_block15a6.CLK1
clock1 => ram_block15a7.CLK1
clock1 => ram_block15a8.CLK1
clock1 => ram_block15a9.CLK1
clock1 => ram_block15a10.CLK1
clock1 => ram_block15a11.CLK1
clock1 => ram_block15a12.CLK1
clock1 => ram_block15a13.CLK1
clock1 => ram_block15a14.CLK1
clock1 => ram_block15a15.CLK1
clocken0 => ram_block15a0.ENA0
clocken0 => ram_block15a1.ENA0
clocken0 => ram_block15a2.ENA0
clocken0 => ram_block15a3.ENA0
clocken0 => ram_block15a4.ENA0
clocken0 => ram_block15a5.ENA0
clocken0 => ram_block15a6.ENA0
clocken0 => ram_block15a7.ENA0
clocken0 => ram_block15a8.ENA0
clocken0 => ram_block15a9.ENA0
clocken0 => ram_block15a10.ENA0
clocken0 => ram_block15a11.ENA0
clocken0 => ram_block15a12.ENA0
clocken0 => ram_block15a13.ENA0
clocken0 => ram_block15a14.ENA0
clocken0 => ram_block15a15.ENA0
clocken1 => ram_block15a0.ENA1
clocken1 => ram_block15a1.ENA1
clocken1 => ram_block15a2.ENA1
clocken1 => ram_block15a3.ENA1
clocken1 => ram_block15a4.ENA1
clocken1 => ram_block15a5.ENA1
clocken1 => ram_block15a6.ENA1
clocken1 => ram_block15a7.ENA1
clocken1 => ram_block15a8.ENA1
clocken1 => ram_block15a9.ENA1
clocken1 => ram_block15a10.ENA1
clocken1 => ram_block15a11.ENA1
clocken1 => ram_block15a12.ENA1
clocken1 => ram_block15a13.ENA1
clocken1 => ram_block15a14.ENA1
clocken1 => ram_block15a15.ENA1
data_a[0] => ram_block15a0.PORTADATAIN
data_a[1] => ram_block15a1.PORTADATAIN
data_a[2] => ram_block15a2.PORTADATAIN
data_a[3] => ram_block15a3.PORTADATAIN
data_a[4] => ram_block15a4.PORTADATAIN
data_a[5] => ram_block15a5.PORTADATAIN
data_a[6] => ram_block15a6.PORTADATAIN
data_a[7] => ram_block15a7.PORTADATAIN
data_a[8] => ram_block15a8.PORTADATAIN
data_a[9] => ram_block15a9.PORTADATAIN
data_a[10] => ram_block15a10.PORTADATAIN
data_a[11] => ram_block15a11.PORTADATAIN
data_a[12] => ram_block15a12.PORTADATAIN
data_a[13] => ram_block15a13.PORTADATAIN
data_a[14] => ram_block15a14.PORTADATAIN
data_a[15] => ram_block15a15.PORTADATAIN
data_b[0] => ram_block15a0.PORTBDATAIN
data_b[1] => ram_block15a1.PORTBDATAIN
data_b[2] => ram_block15a2.PORTBDATAIN
data_b[3] => ram_block15a3.PORTBDATAIN
data_b[4] => ram_block15a4.PORTBDATAIN
data_b[5] => ram_block15a5.PORTBDATAIN
data_b[6] => ram_block15a6.PORTBDATAIN
data_b[7] => ram_block15a7.PORTBDATAIN
data_b[8] => ram_block15a8.PORTBDATAIN
data_b[9] => ram_block15a9.PORTBDATAIN
data_b[10] => ram_block15a10.PORTBDATAIN
data_b[11] => ram_block15a11.PORTBDATAIN
data_b[12] => ram_block15a12.PORTBDATAIN
data_b[13] => ram_block15a13.PORTBDATAIN
data_b[14] => ram_block15a14.PORTBDATAIN
data_b[15] => ram_block15a15.PORTBDATAIN
q_a[0] <= ram_block15a0.PORTADATAOUT
q_a[1] <= ram_block15a1.PORTADATAOUT
q_a[2] <= ram_block15a2.PORTADATAOUT
q_a[3] <= ram_block15a3.PORTADATAOUT
q_a[4] <= ram_block15a4.PORTADATAOUT
q_a[5] <= ram_block15a5.PORTADATAOUT
q_a[6] <= ram_block15a6.PORTADATAOUT
q_a[7] <= ram_block15a7.PORTADATAOUT
q_a[8] <= ram_block15a8.PORTADATAOUT
q_a[9] <= ram_block15a9.PORTADATAOUT
q_a[10] <= ram_block15a10.PORTADATAOUT
q_a[11] <= ram_block15a11.PORTADATAOUT
q_a[12] <= ram_block15a12.PORTADATAOUT
q_a[13] <= ram_block15a13.PORTADATAOUT
q_a[14] <= ram_block15a14.PORTADATAOUT
q_a[15] <= ram_block15a15.PORTADATAOUT
q_b[0] <= ram_block15a0.PORTBDATAOUT
q_b[1] <= ram_block15a1.PORTBDATAOUT
q_b[2] <= ram_block15a2.PORTBDATAOUT
q_b[3] <= ram_block15a3.PORTBDATAOUT
q_b[4] <= ram_block15a4.PORTBDATAOUT
q_b[5] <= ram_block15a5.PORTBDATAOUT
q_b[6] <= ram_block15a6.PORTBDATAOUT
q_b[7] <= ram_block15a7.PORTBDATAOUT
q_b[8] <= ram_block15a8.PORTBDATAOUT
q_b[9] <= ram_block15a9.PORTBDATAOUT
q_b[10] <= ram_block15a10.PORTBDATAOUT
q_b[11] <= ram_block15a11.PORTBDATAOUT
q_b[12] <= ram_block15a12.PORTBDATAOUT
q_b[13] <= ram_block15a13.PORTBDATAOUT
q_b[14] <= ram_block15a14.PORTBDATAOUT
q_b[15] <= ram_block15a15.PORTBDATAOUT
wren_a => ram_block15a0.PORTAWE
wren_a => ram_block15a1.PORTAWE
wren_a => ram_block15a2.PORTAWE
wren_a => ram_block15a3.PORTAWE
wren_a => ram_block15a4.PORTAWE
wren_a => ram_block15a5.PORTAWE
wren_a => ram_block15a6.PORTAWE
wren_a => ram_block15a7.PORTAWE
wren_a => ram_block15a8.PORTAWE
wren_a => ram_block15a9.PORTAWE
wren_a => ram_block15a10.PORTAWE
wren_a => ram_block15a11.PORTAWE
wren_a => ram_block15a12.PORTAWE
wren_a => ram_block15a13.PORTAWE
wren_a => ram_block15a14.PORTAWE
wren_a => ram_block15a15.PORTAWE
wren_b => ram_block15a0.PORTBRE
wren_b => ram_block15a1.PORTBRE
wren_b => ram_block15a2.PORTBRE
wren_b => ram_block15a3.PORTBRE
wren_b => ram_block15a4.PORTBRE
wren_b => ram_block15a5.PORTBRE
wren_b => ram_block15a6.PORTBRE
wren_b => ram_block15a7.PORTBRE
wren_b => ram_block15a8.PORTBRE
wren_b => ram_block15a9.PORTBRE
wren_b => ram_block15a10.PORTBRE
wren_b => ram_block15a11.PORTBRE
wren_b => ram_block15a12.PORTBRE
wren_b => ram_block15a13.PORTBRE
wren_b => ram_block15a14.PORTBRE
wren_b => ram_block15a15.PORTBRE


|sdr_test|sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|dffpipe_c2e:rdaclr
clock => dffe16a[0].CLK
d[0] => dffe16a[0].IN0
q[0] <= dffe16a[0].DB_MAX_OUTPUT_PORT_TYPE


|sdr_test|sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|alt_synch_pipe_fv7:rs_dgwp
clock => dffpipe_909:dffpipe17.clock
d[0] => dffpipe_909:dffpipe17.d[0]
d[1] => dffpipe_909:dffpipe17.d[1]
d[2] => dffpipe_909:dffpipe17.d[2]
d[3] => dffpipe_909:dffpipe17.d[3]
d[4] => dffpipe_909:dffpipe17.d[4]
d[5] => dffpipe_909:dffpipe17.d[5]
d[6] => dffpipe_909:dffpipe17.d[6]
d[7] => dffpipe_909:dffpipe17.d[7]
d[8] => dffpipe_909:dffpipe17.d[8]
d[9] => dffpipe_909:dffpipe17.d[9]
q[0] <= dffpipe_909:dffpipe17.q[0]
q[1] <= dffpipe_909:dffpipe17.q[1]
q[2] <= dffpipe_909:dffpipe17.q[2]
q[3] <= dffpipe_909:dffpipe17.q[3]
q[4] <= dffpipe_909:dffpipe17.q[4]
q[5] <= dffpipe_909:dffpipe17.q[5]
q[6] <= dffpipe_909:dffpipe17.q[6]
q[7] <= dffpipe_909:dffpipe17.q[7]
q[8] <= dffpipe_909:dffpipe17.q[8]
q[9] <= dffpipe_909:dffpipe17.q[9]


|sdr_test|sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|alt_synch_pipe_fv7:rs_dgwp|dffpipe_909:dffpipe17
clock => dffe18a[9].CLK
clock => dffe18a[8].CLK
clock => dffe18a[7].CLK
clock => dffe18a[6].CLK
clock => dffe18a[5].CLK
clock => dffe18a[4].CLK
clock => dffe18a[3].CLK
clock => dffe18a[2].CLK
clock => dffe18a[1].CLK
clock => dffe18a[0].CLK
d[0] => dffe18a[0].IN0
d[1] => dffe18a[1].IN0
d[2] => dffe18a[2].IN0
d[3] => dffe18a[3].IN0
d[4] => dffe18a[4].IN0
d[5] => dffe18a[5].IN0
d[6] => dffe18a[6].IN0
d[7] => dffe18a[7].IN0
d[8] => dffe18a[8].IN0
d[9] => dffe18a[9].IN0
q[0] <= dffe18a[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffe18a[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffe18a[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffe18a[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffe18a[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffe18a[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffe18a[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffe18a[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= dffe18a[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= dffe18a[9].DB_MAX_OUTPUT_PORT_TYPE


|sdr_test|sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|dffpipe_909:ws_brp
clock => dffe18a[9].CLK
clock => dffe18a[8].CLK
clock => dffe18a[7].CLK
clock => dffe18a[6].CLK
clock => dffe18a[5].CLK
clock => dffe18a[4].CLK
clock => dffe18a[3].CLK
clock => dffe18a[2].CLK
clock => dffe18a[1].CLK
clock => dffe18a[0].CLK
d[0] => dffe18a[0].IN0
d[1] => dffe18a[1].IN0
d[2] => dffe18a[2].IN0
d[3] => dffe18a[3].IN0
d[4] => dffe18a[4].IN0
d[5] => dffe18a[5].IN0
d[6] => dffe18a[6].IN0
d[7] => dffe18a[7].IN0
d[8] => dffe18a[8].IN0
d[9] => dffe18a[9].IN0
q[0] <= dffe18a[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffe18a[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffe18a[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffe18a[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffe18a[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffe18a[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffe18a[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffe18a[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= dffe18a[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= dffe18a[9].DB_MAX_OUTPUT_PORT_TYPE


|sdr_test|sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1: