sdr_test.hier_info

来自「sdram读写」· HIER_INFO 代码 · 共 1,777 行 · 第 1/5 页

q[4] <= counter7a[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= counter7a[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= counter7a[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= counter7a[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= counter7a[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= counter7a[9].DB_MAX_OUTPUT_PORT_TYPE


|sdr_test|sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|a_graycounter_d2c:wrptr_g1p
clock => counter8a0.CLK
clock => counter8a1.CLK
clock => counter8a2.CLK
clock => counter8a3.CLK
clock => counter8a4.CLK
clock => counter8a5.CLK
clock => counter8a6.CLK
clock => counter8a7.CLK
clock => counter8a8.CLK
clock => counter8a9.CLK
clock => parity9.CLK
clock => sub_parity10a[2].CLK
clock => sub_parity10a[1].CLK
clock => sub_parity10a[0].CLK
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => cntr_cout[0].IN0
cnt_en => parity_cout.IN1
q[0] <= counter8a0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= counter8a1.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= counter8a2.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= counter8a3.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= counter8a4.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= counter8a5.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= counter8a6.DB_MAX_OUTPUT_PORT_TYPE
q[7] <= counter8a7.DB_MAX_OUTPUT_PORT_TYPE
q[8] <= counter8a8.DB_MAX_OUTPUT_PORT_TYPE
q[9] <= counter8a9.DB_MAX_OUTPUT_PORT_TYPE


|sdr_test|sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|a_graycounter_c2c:wrptr_gp
clock => counter13a[9].CLK
clock => counter13a[8].CLK
clock => counter13a[7].CLK
clock => counter13a[6].CLK
clock => counter13a[5].CLK
clock => counter13a[4].CLK
clock => counter13a[3].CLK
clock => counter13a[2].CLK
clock => counter13a[1].CLK
clock => counter13a[0].CLK
clock => parity11.CLK
clock => sub_parity12a0.CLK
clock => sub_parity12a1.CLK
clock => sub_parity12a2.CLK
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => cntr_cout[0].IN0
cnt_en => parity_cout.IN1
q[0] <= counter13a[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= counter13a[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= counter13a[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= counter13a[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= counter13a[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= counter13a[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= counter13a[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= counter13a[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= counter13a[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= counter13a[9].DB_MAX_OUTPUT_PORT_TYPE


|sdr_test|sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|altsyncram_3j01:fifo_ram
address_a[0] => altsyncram_e7e1:altsyncram14.address_b[0]
address_a[1] => altsyncram_e7e1:altsyncram14.address_b[1]
address_a[2] => altsyncram_e7e1:altsyncram14.address_b[2]
address_a[3] => altsyncram_e7e1:altsyncram14.address_b[3]
address_a[4] => altsyncram_e7e1:altsyncram14.address_b[4]
address_a[5] => altsyncram_e7e1:altsyncram14.address_b[5]
address_a[6] => altsyncram_e7e1:altsyncram14.address_b[6]
address_a[7] => altsyncram_e7e1:altsyncram14.address_b[7]
address_a[8] => altsyncram_e7e1:altsyncram14.address_b[8]
address_b[0] => altsyncram_e7e1:altsyncram14.address_a[0]
address_b[1] => altsyncram_e7e1:altsyncram14.address_a[1]
address_b[2] => altsyncram_e7e1:altsyncram14.address_a[2]
address_b[3] => altsyncram_e7e1:altsyncram14.address_a[3]
address_b[4] => altsyncram_e7e1:altsyncram14.address_a[4]
address_b[5] => altsyncram_e7e1:altsyncram14.address_a[5]
address_b[6] => altsyncram_e7e1:altsyncram14.address_a[6]
address_b[7] => altsyncram_e7e1:altsyncram14.address_a[7]
address_b[8] => altsyncram_e7e1:altsyncram14.address_a[8]
addressstall_b => altsyncram_e7e1:altsyncram14.addressstall_a
clock0 => altsyncram_e7e1:altsyncram14.clock1
clock1 => altsyncram_e7e1:altsyncram14.clock0
clocken1 => altsyncram_e7e1:altsyncram14.clocken0
data_a[0] => altsyncram_e7e1:altsyncram14.data_b[0]
data_a[1] => altsyncram_e7e1:altsyncram14.data_b[1]
data_a[2] => altsyncram_e7e1:altsyncram14.data_b[2]
data_a[3] => altsyncram_e7e1:altsyncram14.data_b[3]
data_a[4] => altsyncram_e7e1:altsyncram14.data_b[4]
data_a[5] => altsyncram_e7e1:altsyncram14.data_b[5]
data_a[6] => altsyncram_e7e1:altsyncram14.data_b[6]
data_a[7] => altsyncram_e7e1:altsyncram14.data_b[7]
data_a[8] => altsyncram_e7e1:altsyncram14.data_b[8]
data_a[9] => altsyncram_e7e1:altsyncram14.data_b[9]
data_a[10] => altsyncram_e7e1:altsyncram14.data_b[10]
data_a[11] => altsyncram_e7e1:altsyncram14.data_b[11]
data_a[12] => altsyncram_e7e1:altsyncram14.data_b[12]
data_a[13] => altsyncram_e7e1:altsyncram14.data_b[13]
data_a[14] => altsyncram_e7e1:altsyncram14.data_b[14]
data_a[15] => altsyncram_e7e1:altsyncram14.data_b[15]
q_b[0] <= altsyncram_e7e1:altsyncram14.q_a[0]
q_b[1] <= altsyncram_e7e1:altsyncram14.q_a[1]
q_b[2] <= altsyncram_e7e1:altsyncram14.q_a[2]
q_b[3] <= altsyncram_e7e1:altsyncram14.q_a[3]
q_b[4] <= altsyncram_e7e1:altsyncram14.q_a[4]
q_b[5] <= altsyncram_e7e1:altsyncram14.q_a[5]
q_b[6] <= altsyncram_e7e1:altsyncram14.q_a[6]
q_b[7] <= altsyncram_e7e1:altsyncram14.q_a[7]
q_b[8] <= altsyncram_e7e1:altsyncram14.q_a[8]
q_b[9] <= altsyncram_e7e1:altsyncram14.q_a[9]
q_b[10] <= altsyncram_e7e1:altsyncram14.q_a[10]
q_b[11] <= altsyncram_e7e1:altsyncram14.q_a[11]
q_b[12] <= altsyncram_e7e1:altsyncram14.q_a[12]
q_b[13] <= altsyncram_e7e1:altsyncram14.q_a[13]
q_b[14] <= altsyncram_e7e1:altsyncram14.q_a[14]
q_b[15] <= altsyncram_e7e1:altsyncram14.q_a[15]
wren_a => altsyncram_e7e1:altsyncram14.clocken1
wren_a => altsyncram_e7e1:altsyncram14.wren_b


|sdr_test|sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|altsyncram_3j01:fifo_ram|altsyncram_e7e1:altsyncram14
address_a[0] => ram_block15a0.PORTAADDR
address_a[0] => ram_block15a1.PORTAADDR
address_a[0] => ram_block15a2.PORTAADDR
address_a[0] => ram_block15a3.PORTAADDR
address_a[0] => ram_block15a4.PORTAADDR
address_a[0] => ram_block15a5.PORTAADDR
address_a[0] => ram_block15a6.PORTAADDR
address_a[0] => ram_block15a7.PORTAADDR
address_a[0] => ram_block15a8.PORTAADDR
address_a[0] => ram_block15a9.PORTAADDR
address_a[0] => ram_block15a10.PORTAADDR
address_a[0] => ram_block15a11.PORTAADDR
address_a[0] => ram_block15a12.PORTAADDR
address_a[0] => ram_block15a13.PORTAADDR
address_a[0] => ram_block15a14.PORTAADDR
address_a[0] => ram_block15a15.PORTAADDR
address_a[1] => ram_block15a0.PORTAADDR1
address_a[1] => ram_block15a1.PORTAADDR1
address_a[1] => ram_block15a2.PORTAADDR1
address_a[1] => ram_block15a3.PORTAADDR1
address_a[1] => ram_block15a4.PORTAADDR1
address_a[1] => ram_block15a5.PORTAADDR1
address_a[1] => ram_block15a6.PORTAADDR1
address_a[1] => ram_block15a7.PORTAADDR1
address_a[1] => ram_block15a8.PORTAADDR1
address_a[1] => ram_block15a9.PORTAADDR1
address_a[1] => ram_block15a10.PORTAADDR1
address_a[1] => ram_block15a11.PORTAADDR1
address_a[1] => ram_block15a12.PORTAADDR1
address_a[1] => ram_block15a13.PORTAADDR1
address_a[1] => ram_block15a14.PORTAADDR1
address_a[1] => ram_block15a15.PORTAADDR1
address_a[2] => ram_block15a0.PORTAADDR2
address_a[2] => ram_block15a1.PORTAADDR2
address_a[2] => ram_block15a2.PORTAADDR2
address_a[2] => ram_block15a3.PORTAADDR2
address_a[2] => ram_block15a4.PORTAADDR2
address_a[2] => ram_block15a5.PORTAADDR2
address_a[2] => ram_block15a6.PORTAADDR2
address_a[2] => ram_block15a7.PORTAADDR2
address_a[2] => ram_block15a8.PORTAADDR2
address_a[2] => ram_block15a9.PORTAADDR2
address_a[2] => ram_block15a10.PORTAADDR2
address_a[2] => ram_block15a11.PORTAADDR2
address_a[2] => ram_block15a12.PORTAADDR2
address_a[2] => ram_block15a13.PORTAADDR2
address_a[2] => ram_block15a14.PORTAADDR2
address_a[2] => ram_block15a15.PORTAADDR2
address_a[3] => ram_block15a0.PORTAADDR3
address_a[3] => ram_block15a1.PORTAADDR3
address_a[3] => ram_block15a2.PORTAADDR3
address_a[3] => ram_block15a3.PORTAADDR3
address_a[3] => ram_block15a4.PORTAADDR3
address_a[3] => ram_block15a5.PORTAADDR3
address_a[3] => ram_block15a6.PORTAADDR3
address_a[3] => ram_block15a7.PORTAADDR3
address_a[3] => ram_block15a8.PORTAADDR3
address_a[3] => ram_block15a9.PORTAADDR3
address_a[3] => ram_block15a10.PORTAADDR3
address_a[3] => ram_block15a11.PORTAADDR3
address_a[3] => ram_block15a12.PORTAADDR3
address_a[3] => ram_block15a13.PORTAADDR3
address_a[3] => ram_block15a14.PORTAADDR3
address_a[3] => ram_block15a15.PORTAADDR3
address_a[4] => ram_block15a0.PORTAADDR4
address_a[4] => ram_block15a1.PORTAADDR4
address_a[4] => ram_block15a2.PORTAADDR4
address_a[4] => ram_block15a3.PORTAADDR4
address_a[4] => ram_block15a4.PORTAADDR4
address_a[4] => ram_block15a5.PORTAADDR4
address_a[4] => ram_block15a6.PORTAADDR4
address_a[4] => ram_block15a7.PORTAADDR4
address_a[4] => ram_block15a8.PORTAADDR4
address_a[4] => ram_block15a9.PORTAADDR4
address_a[4] => ram_block15a10.PORTAADDR4
address_a[4] => ram_block15a11.PORTAADDR4
address_a[4] => ram_block15a12.PORTAADDR4
address_a[4] => ram_block15a13.PORTAADDR4
address_a[4] => ram_block15a14.PORTAADDR4
address_a[4] => ram_block15a15.PORTAADDR4
address_a[5] => ram_block15a0.PORTAADDR5
address_a[5] => ram_block15a1.PORTAADDR5
address_a[5] => ram_block15a2.PORTAADDR5
address_a[5] => ram_block15a3.PORTAADDR5
address_a[5] => ram_block15a4.PORTAADDR5
address_a[5] => ram_block15a5.PORTAADDR5
address_a[5] => ram_block15a6.PORTAADDR5
address_a[5] => ram_block15a7.PORTAADDR5
address_a[5] => ram_block15a8.PORTAADDR5
address_a[5] => ram_block15a9.PORTAADDR5
address_a[5] => ram_block15a10.PORTAADDR5
address_a[5] => ram_block15a11.PORTAADDR5
address_a[5] => ram_block15a12.PORTAADDR5
address_a[5] => ram_block15a13.PORTAADDR5
address_a[5] => ram_block15a14.PORTAADDR5
address_a[5] => ram_block15a15.PORTAADDR5
address_a[6] => ram_block15a0.PORTAADDR6
address_a[6] => ram_block15a1.PORTAADDR6
address_a[6] => ram_block15a2.PORTAADDR6
address_a[6] => ram_block15a3.PORTAADDR6
address_a[6] => ram_block15a4.PORTAADDR6
address_a[6] => ram_block15a5.PORTAADDR6
address_a[6] => ram_block15a6.PORTAADDR6
address_a[6] => ram_block15a7.PORTAADDR6
address_a[6] => ram_block15a8.PORTAADDR6
address_a[6] => ram_block15a9.PORTAADDR6
address_a[6] => ram_block15a10.PORTAADDR6
address_a[6] => ram_block15a11.PORTAADDR6
address_a[6] => ram_block15a12.PORTAADDR6
address_a[6] => ram_block15a13.PORTAADDR6
address_a[6] => ram_block15a14.PORTAADDR6
address_a[6] => ram_block15a15.PORTAADDR6
address_a[7] => ram_block15a0.PORTAADDR7
address_a[7] => ram_block15a1.PORTAADDR7
address_a[7] => ram_block15a2.PORTAADDR7
address_a[7] => ram_block15a3.PORTAADDR7
address_a[7] => ram_block15a4.PORTAADDR7
address_a[7] => ram_block15a5.PORTAADDR7
address_a[7] => ram_block15a6.PORTAADDR7
address_a[7] => ram_block15a7.PORTAADDR7
address_a[7] => ram_block15a8.PORTAADDR7
address_a[7] => ram_block15a9.PORTAADDR7
address_a[7] => ram_block15a10.PORTAADDR7
address_a[7] => ram_block15a11.PORTAADDR7
address_a[7] => ram_block15a12.PORTAADDR7
address_a[7] => ram_block15a13.PORTAADDR7
address_a[7] => ram_block15a14.PORTAADDR7
address_a[7] => ram_block15a15.PORTAADDR7
address_a[8] => ram_block15a0.PORTAADDR8
address_a[8] => ram_block15a1.PORTAADDR8
address_a[8] => ram_block15a2.PORTAADDR8
address_a[8] => ram_block15a3.PORTAADDR8
address_a[8] => ram_block15a4.PORTAADDR8
address_a[8] => ram_block15a5.PORTAADDR8
address_a[8] => ram_block15a6.PORTAADDR8
address_a[8] => ram_block15a7.PORTAADDR8
address_a[8] => ram_block15a8.PORTAADDR8
address_a[8] => ram_block15a9.PORTAADDR8
address_a[8] => ram_block15a10.PORTAADDR8
address_a[8] => ram_block15a11.PORTAADDR8
address_a[8] => ram_block15a12.PORTAADDR8
address_a[8] => ram_block15a13.PORTAADDR8
address_a[8] => ram_block15a14.PORTAADDR8
address_a[8] => ram_block15a15.PORTAADDR8
address_b[0] => ram_block15a0.PORTBADDR
address_b[0] => ram_block15a1.PORTBADDR
address_b[0] => ram_block15a2.PORTBADDR
address_b[0] => ram_block15a3.PORTBADDR
address_b[0] => ram_block15a4.PORTBADDR
address_b[0] => ram_block15a5.PORTBADDR
address_b[0] => ram_block15a6.PORTBADDR
address_b[0] => ram_block15a7.PORTBADDR
address_b[0] => ram_block15a8.PORTBADDR
address_b[0] => ram_block15a9.PORTBADDR
address_b[0] => ram_block15a10.PORTBADDR
address_b[0] => ram_block15a11.PORTBADDR
address_b[0] => ram_block15a12.PORTBADDR
address_b[0] => ram_block15a13.PORTBADDR
address_b[0] => ram_block15a14.PORTBADDR
address_b[0] => ram_block15a15.PORTBADDR
address_b[1] => ram_block15a0.PORTBADDR1
address_b[1] => ram_block15a1.PORTBADDR1
address_b[1] => ram_block15a2.PORTBADDR1
address_b[1] => ram_block15a3.PORTBADDR1
address_b[1] => ram_block15a4.PORTBADDR1
address_b[1] => ram_block15a5.PORTBADDR1
address_b[1] => ram_block15a6.PORTBADDR1
address_b[1] => ram_block15a7.PORTBADDR1
address_b[1] => ram_block15a8.PORTBADDR1
address_b[1] => ram_block15a9.PORTBADDR1
address_b[1] => ram_block15a10.PORTBADDR1
address_b[1] => ram_block15a11.PORTBADDR1
address_b[1] => ram_block15a12.PORTBADDR1
address_b[1] => ram_block15a13.PORTBADDR1
address_b[1] => ram_block15a14.PORTBADDR1
address_b[1] => ram_block15a15.PORTBADDR1
address_b[2] => ram_block15a0.PORTBADDR2
address_b[2] => ram_block15a1.PORTBADDR2
address_b[2] => ram_block15a2.PORTBADDR2
address_b[2] => ram_block15a3.PORTBADDR2
address_b[2] => ram_block15a4.PORTBADDR2
address_b[2] => ram_block15a5.PORTBADDR2
address_b[2] => ram_block15a6.PORTBADDR2
address_b[2] => ram_block15a7.PORTBADDR2
address_b[2] => ram_block15a8.PORTBADDR2
address_b[2] => ram_block15a9.PORTBADDR2
address_b[2] => ram_block15a10.PORTBADDR2
address_b[2] => ram_block15a11.PORTBADDR2
address_b[2] => ram_block15a12.PORTBADDR2
address_b[2] => ram_block15a13.PORTBADDR2
address_b[2] => ram_block15a14.PORTBADDR2
address_b[2] => ram_block15a15.PORTBADDR2
address_b[3] => ram_block15a0.PORTBADDR3
address_b[3] => ram_block15a1.PORTBADDR3
address_b[3] => ram_block15a2.PORTBADDR3
address_b[3] => ram_block15a3.PORTBADDR3
address_b[3] => ram_block15a4.PORTBADDR3
address_b[3] => ram_block15a5.PORTBADDR3
address_b[3] => ram_block15a6.PORTBADDR3
address_b[3] => ram_block15a7.PORTBADDR3
address_b[3] => ram_block15a8.PORTBADDR3
address_b[3] => ram_block15a9.PORTBADDR3
address_b[3] => ram_block15a10.PORTBADDR3
address_b[3] => ram_block15a11.PORTBADDR3
address_b[3] => ram_block15a12.PORTBADDR3
address_b[3] => ram_block15a13.PORTBADDR3
address_b[3] => ram_block15a14.PORTBADDR3
address_b[3] => ram_block15a15.PORTBADDR3
address_b[4] => ram_block15a0.PORTBADDR4
address_b[4] => ram_block15a1.PORTBADDR4