divider.vhd

来自「用VHDL编写的实现二、三、四分频」· VHDL 代码 · 共 53 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity divider is
  port(clk,clr:in std_logic;
       div2,div3,div4:out std_logic);
end entity;

architecture behavior of divider is
  signal pos_cnt:std_logic_vector(1 downto 0);
  signal neg_cnt:std_logic_vector(1 downto 0);
  signal count:std_logic_vector(1 downto 0);
begin
  process(clk,clr)
  begin
    if clr='1' then count<="00";
    elsif clk'event and clk='1' then
      if count="11" then
         count<="00";
      else
         count<=count+1;
      end if;
    end if;
  end process;
  process(clk,clr)
  begin
    if clr='1' then pos_cnt<="00";
    elsif clk'event and clk='1' then
       case pos_cnt is
         when "00" => pos_cnt<="01";
         when "01" => pos_cnt<="10";
         when "10" => pos_cnt<="00";
         when others=> pos_cnt<="00";
       end case;
    end if;
  end process;
  process(clk,clr)
  begin
    if clr='1' then neg_cnt<="00";
    elsif clk'event and clk='0' then
       case neg_cnt is
         when "00" => neg_cnt<="01";
         when "01" => neg_cnt<="10";
         when "10" => neg_cnt<="00";
         when others => neg_cnt<="00";
       end case;
    end if;
  end process;
  div2<=count(0);
  div3<=not(pos_cnt(1) or neg_cnt(1));
  div4<=count(1);
end;