HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptiv

VHDL/FPGA/Verilog 415 K 181 次下载 2017-06-25

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415 K

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VHDL/FPGA/Verilog

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yangbaochun

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2017-06-25 20:56

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181 次

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HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptiv - 资源详细说明

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptiv - 源码文件列表

本资源包含 37 个源码文件支持在线预览，点击文件名即可查看

readme.txt

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptiv

资源详细信息

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptiv - 资源详细说明

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptiv - 源码文件列表

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