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ramr.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
rami.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
ifft.v
module FFT_Pro(clk20M,clk60M,rst_n,inEn,dataInR,dataInI,outEn,dataOutR,dataOutI,bitIndex);
input clk20M;
input clk60M;
input rst_n;
input inEn;
input [7:0]dataInR;
input [7:0]dataInI;
ou
dataromi.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
dataromr.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
timescale.v
`timescale 1ns / 1ns
timescale.v
`timescale 1ns/10ps
timescale.v
`timescale 1ns / 10ps
tests.v
task show_errors;
begin
$display("\n");
$display(" +--------------------+");
$display(" | Total ERRORS: %0d |", error_cnt);
$display(" +----------
timescale.v
`timescale 1ns / 10ps