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reset.v
//Reset
module reset (
// rst_in_n,
rst_from_cpu_n,
reset_n,
rst_out_n,
rst_out_reg_n);
// wdo
// input rst_in_n;
input rst_from_cpu_n;
output reset_n;
output [31:0] rst_out_n;
interrupt.v
//interrupt
module interrupt (
int_in_n,
int_out_n,
int_mask
);
input [31:0] int_in_n;
output int_out_n;
input [31:0] int_mask;//set 1 to mask the intrrupt source
assign int_o
parallel.v
/***Local Bus Interface*********************************************************/
//外接VSC7324
module parallel_interface (
clock,reset_n,
addr_in,data_in,data_out,ready_n,
l_cmdo,abort_n,lt_f
watchdog.v
//WatchDog counter
module watchdog(
clk,
rst_n,
wdval,
wden,
wdi,
// wdf,
wdo
);
input clk,rst_n;
input wden;//watchdog enable
input wdi;//watchdog refresh
// output wdf;//w
top.v
//说明
//
//本程序用于R8000E 16端口GE线卡
//
//主要功能：
//1、PCI到LocalBus接口、IIC等的转换
// LocalBus接口接VSC7324处理器接口
// IIC接CY22394、24C02、Backplane(风扇单元)
//2、复位、中断及其它控制信号
//
//
//李翔
//2006-04-21
//
mod
conf_if.v
//
//-----------------------------------------------------------------------------
// Title :
// Project :
//-----------------------------------------------------------------------------
cam.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
system.v
//-----------------------------------------------------------------------------
// system.v
//-----------------------------------------------------------------------------
module system
(
system.v
module system
(
fpga_0_RS232_Uart_1_RX_pin,
fpga_0_RS232_Uart_1_TX_pin,
fpga_0_LEDs_4Bit_GPIO_IO_pin,
fpga_0_DIPSWs_4Bit_GPIO_IO_pin,
fpga_0_PushButtons_5Bit_GPIO_IO_pin,
fpga_0_PS2_Port
fc.v
//
//-----------------------------------------------------------------------------
// Title : fifo control module
// Project :
//----------------------------------------------------------