fc.v

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//
//-----------------------------------------------------------------------------
// Title      : fifo control module
// Project    : 
//-----------------------------------------------------------------------------
// File       : fc.v
// Author     : 
// Date       : 07-10-21
//-----------------------------------------------------------------------------
// Description:   fifo control 
//                drop error packet
//-------------------------------------------------------------------------------
 
`timescale 1ns/10ps

module fc(
sys_clk, 
sys_rst_n,
cal_sop_fc, 
cal_eop_fc, 
cal_dat_fc,
cal_mod_fc, 
cal_vld_fc, 
cal_spkt_fc, 
cal_lpkt_fc,
cal_epkt_fc,
fc_afull_cal,
fc_sop_ih, 
fc_eop_ih, 
fc_vld_ih, 
fc_dat_ih, 
fc_mod_ih,  
ih_pb_fc
);

/*-------------------------------------------------------------------*\
                          Parameter Description
\*-------------------------------------------------------------------*/

parameter   D = 2;

/*-------------------------------------------------------------------*\
                            Port Description
\*-------------------------------------------------------------------*/ 

/*--------Global Signals--------*/
input               sys_clk;
input               sys_rst_n;

/*----------IXF_IF I/F----------*/
input               cal_sop_fc;
input               cal_eop_fc;
input     [31:0]    cal_dat_fc;
input     [1:0]     cal_mod_fc;
input               cal_vld_fc;
input               cal_spkt_fc;     //short packet
input               cal_lpkt_fc;     //long  packet
input               cal_epkt_fc;     //error packet
output              fc_afull_cal;

/*---------IXF_ARB I/F----------*/
output              fc_sop_ih;
output              fc_eop_ih;
output              fc_vld_ih;
output    [31:0]    fc_dat_ih;
output    [1:0]     fc_mod_ih;
input               ih_pb_fc;

/*-------------------------------------------------------------------*\
                          Reg/Wire Description
\*-------------------------------------------------------------------*/

reg                 fc_afull_cal;
reg                 fc_sop_ih;
reg                 fc_eop_ih;
reg                 fc_vld_ih;
reg       [31:0]    fc_dat_ih;
reg       [1:0]     fc_mod_ih;             

//register the input singal
reg                 f_cal_sop_fc;
reg                 f_cal_eop_fc;
reg       [31:0]    f_cal_dat_fc;
reg       [1:0]     f_cal_mod_fc;
reg                 f_cal_vld_fc;
reg		    f_cal_err_fc;

//signal with fifo control
reg		    wen;
reg	  [9:0]	    waddr;
reg	  [35:0]    wdat;
reg	  [9:0]	    tmp_waddr;
reg		    drp_pkt;
reg		    eop_d;
wire		    fifo_empty;
reg	  [9:0]	    disp_addr;
reg	  [9:0]	    raddr;
wire	  [35:0]    rdat;
reg		    data_write;
wire	  [35:0]    data_in;
wire		    data_read;
wire	  [35:0]    data_out;
wire		    lb_empty_n;
wire		    lb_afull;
reg		    read_en;
reg		    ren;
reg	  [9:0]     use_frm;

//signal with arbiter
reg                 tmp_sop_ih;
reg                 tmp_eop_ih;
reg                 tmp_vld_ih;
reg       [31:0]    tmp_dat_ih;
reg       [1:0]     tmp_mod_ih;

/*-------------------------------------------------------------------*\
                               Main Codes
\*-------------------------------------------------------------------*/        

//register input signal
always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     begin
       f_cal_sop_fc <= #D 1'b0;
       f_cal_eop_fc <= #D 1'b0;
       f_cal_dat_fc <= #D 32'b0;
       f_cal_mod_fc <= #D 2'b0;
       f_cal_vld_fc <= #D 1'b0;
       f_cal_err_fc <= #D 1'b0;       
     end
  else
     begin
       f_cal_sop_fc <= #D cal_sop_fc;
       f_cal_eop_fc <= #D cal_eop_fc;
       f_cal_dat_fc <= #D cal_dat_fc;
       f_cal_mod_fc <= #D cal_mod_fc;
       f_cal_vld_fc <= #D cal_vld_fc;
       f_cal_err_fc <= #D cal_spkt_fc || cal_lpkt_fc || cal_epkt_fc;
     end
end

/*---------------------------------------------*\
        write to fifo and drop error packet
\*---------------------------------------------*/

//error packet flag
always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     drp_pkt <= #D 1'b0;
  else
     drp_pkt <= #D f_cal_eop_fc && f_cal_vld_fc && f_cal_err_fc;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     eop_d <= #D 1'b0;
  else
     eop_d <= #D f_cal_eop_fc && f_cal_vld_fc;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     wen <= #D 1'b0;
  else
     wen <= #D f_cal_vld_fc;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     waddr <= #D 10'b0;
  else if(drp_pkt)
     waddr <= #D tmp_waddr;
  else if(wen)
     waddr <= #D waddr + 10'd1;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     tmp_waddr <= #D 10'b0;
  else if(~drp_pkt && eop_d)
     tmp_waddr <= #D waddr + 10'd1;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     wdat <= #D 36'b0;
  else
     wdat <= #D {f_cal_sop_fc,f_cal_eop_fc,f_cal_mod_fc,f_cal_dat_fc};
end

//instance dpram1024x36
dpram1024x36 u_dpram1024x36(
    .addra (waddr),
    .addrb (raddr),
    .clka  (sys_clk),
    .clkb  (sys_clk),
    .dina  (wdat),
    .doutb (rdat),
    .enb   (ren),
    .wea   (wen)
    );

//generate fifo afull signal and fifo empty signal
assign fifo_empty = tmp_waddr == raddr;

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     disp_addr <= #D 10'b0;
  else
     disp_addr <= #D waddr - raddr;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     fc_afull_cal <= #D 1'b0;
  else if(disp_addr[9:5] >= 5'b1_1111)
     fc_afull_cal <= #D 1'b1;
  else if(disp_addr[9:5] <= 5'b1_1101)
     fc_afull_cal <= #D 1'b0; 
end

//write to lb_fifo_5cell
always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     use_frm <= #D 10'b0;
  else
     use_frm <= #D tmp_waddr - raddr;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     read_en <= #D 1'b1;
  else if(use_frm < 10'd4)
     read_en <= #D ~read_en;
  else
     read_en <= #D 1'b1;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     ren <= #D 1'b0;
  else
     ren <= #D read_en && ~fifo_empty && ~lb_afull;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     raddr <= #D 10'b0;
  else if(ren)
     raddr <= #D raddr + 10'd1;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     data_write <= #D 1'b0;
  else
     data_write <= #D ren;
end

assign data_in = rdat;

//instance lb_fifo_5cell
lb_fifo_5cell #(36,D) u_lb_fifo_5cell (
    .sys_clk    (sys_clk),     
    .sys_rst_n  (sys_rst_n),    
    .data_in    (data_in),
    .data_read  (data_read),    
    .data_out   (data_out),
    .data_write (data_write),   

    .full_cell0 (lb_empty_n), 
    .full_cell1 (),             
    .full_cell2 (lb_afull),    
    .full_cell3 (),
    .full_cell4 ()            
    );

//read from the lb_fifo_5cell

assign data_read = lb_empty_n && ~ih_pb_fc;

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     tmp_sop_ih <= #D 1'b0; 
  else
     tmp_sop_ih <= #D data_out[35] && data_read;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     tmp_eop_ih <= #D 1'b0;
  else
     tmp_eop_ih <= #D data_out[34] && data_read;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     tmp_mod_ih <= #D 2'b0;
  else if(data_read)
     tmp_mod_ih <= #D data_out[33:32];
  else
  	 tmp_mod_ih <= #D 2'b0;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     tmp_vld_ih <= #D 1'b0;
  else
     tmp_vld_ih <= #D data_read;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     tmp_dat_ih <= #D 32'b0;
  else
     tmp_dat_ih <= #D data_out[31:0];
end

//send packet out
always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     begin
       fc_sop_ih <= #D 1'b0;
       fc_eop_ih <= #D 1'b0;
       fc_vld_ih <= #D 1'b0;
       fc_dat_ih <= #D 32'b0;
       fc_mod_ih <= #D 2'b0;        
     end
  else
     begin
       fc_sop_ih <= #D tmp_sop_ih && tmp_vld_ih;
       fc_eop_ih <= #D tmp_eop_ih && tmp_vld_ih;
       fc_vld_ih <= #D tmp_vld_ih;
       fc_dat_ih <= #D tmp_dat_ih;
       fc_mod_ih <= #D tmp_mod_ih;
     end
end

endmodule