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V 的代码
all.v
module all (a,b,y);
input [7:0] a,b;
output [8:0] y;
function [8:0] add_It_10;
input [7:0] a,b;
reg [7:0] temp;
begin
if(b
full_adder_1.v
module full_adder(a,b,cin,out,carry);
input a,b,cin;
output out,carry;
reg out,carry;
reg t1,t2,t3;
always@
(a or b or cin)begin
out = a^b^cin;
t1 = a&cin;
adc_16bit.v
// 16-bit Analogue-Digital Converter
//
// +-----------------------------+
// | Copyright 1996 DOULOS |
// | designer : Tim Pagden |
// | opened: 7 Jun 1996 |
// +----------
mult_select.v
`include "oc8051_timescale.v"
// synopsys translate_on
`include "oc8051_defines.v"
module oc8051_alu_src1_sel (sel, immediate, acc, ram, ext, des);
//
// sel (in) select signals (
cla_8bits.v
module cla_8bits(a,b,c0,c8,s);
input [7:0] a,b;
input c0;
output c8;
output [7:0] s;
reg [7:0] p,q;
reg [7:1] c;
reg [7:
mul16.v
module mult16(clk,resetb,start,done,ain,bin,yout);
parameter N=16;
input clk;
input resetb;
input start;
input [N-1:0] ain;
input [N-1:0] bin;
output
full_adder_2.v
`include "half_adder_1.v"
module full_adder(a,b,cin,out,carry);
input a,b,cin;
output carry,out;
half_adder m1 (a,b,out1,carry1);
half_adder m2 (cin,out1,out,carry2);
or m3 (carry,carry1,carr
fifo_2.v
// Synchronous FIFO. 4 x 16 bit words.
//
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
input clk;
input rstp;
input [15:0] din;
input readp;
input writep;
output [15:
encoder8x3.v
module encoder8x3(in,out);
input [7:0] in;
output [2:0] out;
reg [2:0] out;
reg [2:0] i;
always @(in)
begin
for(i=0;i
half_adder_2.v
module half_adder(a,b,out,carry);
input a,b;
output out,carry;
assign out=a^b;
assign carry=a&b;
endmodule