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t_divider.ant
-- D:\FPGA\仿真\DIVIDER_定点除法器
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Thu Jul 13 10:59:57 2006
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE
t_compact.ant
-- D:\FPGA\仿真\DIVIDER
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Mon May 29 11:41:17 2006
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.S
t_divider.tdo
## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-PAR Simulation
##
vlib work
## Compile Post-PAR Model for Module devider
vcom -87 -explicit devider_timesim.v
t_compact.tdo
## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-PAR Simulation
##
vlib work
## Compile Post-PAR Model for Module compact_divider
vcom -87 -explicit compact_d
t_compact.fdo
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Mon May 29 11:41:18 中国标准时间 2006
##
vlib work
vcom -93 -explicit compact_divider.vhdl
vcom -93 -explicit t_compact.
t_divider.udo
-- ProjNav VHDL simula<mark>t</mark>ion <mark>t</mark>empla<mark>t</mark>e: <mark>t</mark>_divider.udo
-- You may edi<mark>t</mark> <mark>t</mark>his file af<mark>t</mark>er <mark>t</mark>he line <mark>t</mark>ha<mark>t</mark> s<mark>t</mark>ar<mark>t</mark>s wi<mark>t</mark>h
-- '-- S<mark>T</mark>AR<mark>T</mark>' <mark>t</mark>o cus<mark>t</mark>omize your simula<mark>t</mark>ion
-- S<mark>T</m ...
t_divider.jhd
MODULE t_divider
SUBMODULE devider
t_divider.vhw
-- D:\FPGA\仿真\DIVIDER_定点除法器
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Jul 13 10:59:57 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test