t_compact.ant

本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.

-- D:\FPGA\仿真\DIVIDER
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Mon May 29 11:41:17 2006

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY t_compact IS
END t_compact;

ARCHITECTURE testbench_arch OF t_compact IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "d:\fpga\仿真\divider\t_compact.ano";
	COMPONENT compact_divider
		GENERIC (
			n : INTEGER
		);
		PORT (
			a : In  INTEGER RANGE 0 TO 15;
			b : In  INTEGER RANGE 0 TO 15;
			y : Out  std_logic_vector (3 DOWNTO 0);
			rest : Out  INTEGER RANGE 0 TO 15;
			err : Out  std_logic
		);
	END COMPONENT;

	SIGNAL a : INTEGER RANGE 0 TO 15;
	SIGNAL b : INTEGER RANGE 0 TO 15;
	SIGNAL y : std_logic_vector (3 DOWNTO 0);
	SIGNAL rest : INTEGER RANGE 0 TO 15;
	SIGNAL err : std_logic;

BEGIN
	UUT : compact_divider
	GENERIC MAP (
		n => 3
	)
	PORT MAP (
		a => a,
		b => b,
		y => y,
		rest => rest,
		err => err
	);

	PROCESS -- Annotate outputs process
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_y(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",y,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, y);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_rest(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",rest,"));
			STD.TEXTIO.write(TX_LOC, rest);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_err(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",err,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, err);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CHECK_LOOP : LOOP
		WAIT FOR 50 us;
		TX_TIME := TX_TIME + 50;
		ANNOTATE_y(TX_TIME);
		ANNOTATE_rest(TX_TIME);
		ANNOTATE_err(TX_TIME);
		WAIT FOR 50 us;
		TX_TIME := TX_TIME + 50;
		END LOOP CHECK_LOOP;
	END PROCESS;

	PROCESS
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		a <= transport 0; -- 0
		b <= transport 0; -- 0
		-- --------------------
		WAIT FOR 100 us; -- Time=100 us
		a <= transport 1; -- 1
		b <= transport 0; -- 0
		-- --------------------
		WAIT FOR 100 us; -- Time=200 us
		a <= transport 2; -- 2
		b <= transport 1; -- 1
		-- --------------------
		WAIT FOR 100 us; -- Time=300 us
		a <= transport 3; -- 3
		b <= transport 2; -- 2
		-- --------------------
		WAIT FOR 100 us; -- Time=400 us
		a <= transport 4; -- 4
		b <= transport 0; -- 0
		-- --------------------
		WAIT FOR 100 us; -- Time=500 us
		a <= transport 5; -- 5
		b <= transport 1; -- 1
		-- --------------------
		WAIT FOR 100 us; -- Time=600 us
		a <= transport 6; -- 6
		b <= transport 2; -- 2
		-- --------------------
		WAIT FOR 100 us; -- Time=700 us
		a <= transport 7; -- 7
		b <= transport 0; -- 0
		-- --------------------
		WAIT FOR 100 us; -- Time=800 us
		b <= transport 1; -- 1
		-- --------------------
		WAIT FOR 500 us; -- Time=1300 us
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION compact_divider_cfg OF t_compact IS
	FOR testbench_arch
	END FOR;
END compact_divider_cfg;