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uart0.c
/*************************************************************************************
** Copyright (c) 2007,XXXXXXXXXXXXXXXXXXXXXXXXXXXXX
** http://XXXXXXXXXXXXXXXXX
**文件名称：Timer.C
**功能说明：与定时器相
layer0.tlg
@N:"E:\modelsim\vr_fifo\src\vr_fifo_rtl.vhd":15:7:15:13|Synthesizing work.vr_fifo.rtl
Post processing for work.vr_fifo.rtl
@N: CL134 :"E:\modelsim\vr_fifo\src\vr_fifo_rtl.vhd":41:9:41:16|Found RAM
layer0.sro
# Created by Synplify VHDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Fri Jul 28 23:38:28 2
system_0.bsf
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 464 1424)
(text "system_0" (rect 4 0 70 16)(font "Arial" (font_size 10)))
(text "inst" (rect 4 1408 28 1424)(font "Arial"))
(port
(pt 0 32)
(
system_0.bsf
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 464 1424)
(text "system_0" (rect 4 0 70 16)(font "Arial" (font_size 10)))
(text "inst" (rect 4 1408 28 1424)(font "Arial"))
(port
(pt 0 32)
(
audio_0.v
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
timer0.plg
Build target 'Target 1'
compiling main.c...
linking...
"timer1" - 0 Error(s), 0 Warning(s).
external0.opt
### uVision2 Project, (C) Keil Software
### Do not modify !
cExt (*.c)
aExt (*.a*; *.src)
oExt (*.obj)
lExt (*.lib)
tExt (*.txt)
pExt (*.plm)
CppX (*.cpp)
DaveTm { 0,0,0,0,0,0,0,0 }