layer0.tlg

来自「可预取的fifo 的fpga 设计代码」· TLG 代码 · 共 4 行

@N:"E:\modelsim\vr_fifo\src\vr_fifo_rtl.vhd":15:7:15:13|Synthesizing work.vr_fifo.rtl 
Post processing for work.vr_fifo.rtl
@N: CL134 :"E:\modelsim\vr_fifo\src\vr_fifo_rtl.vhd":41:9:41:16|Found RAM fifo_ary, depth=16, width=8