layer0.sro

可预取的fifo 的fpga 设计代码

# Created by Synplify VHDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Fri Jul 28 23:38:28 2006
#
#
#OPTIONS:"|-mixedhdl|-top|vr_fifo|-layerid|0|-primux|-fixsmult|-sdff_counter|-infer_seqShift|-nram|-divnmod|-autosm|-fid2|-sharing|on|-encrypt|-ui|-lite|-pro|-ram|-ignore_undefined_lib|-ll|2000|-lib|work"
#CUR:"D:\\synplicity\\fpga_81\\bin\\c_vhdl.exe":1115125640
#CUR:"D:\\synplicity\\fpga_81\\lib\\vhd\\location.map":1114701536
#CUR:"D:\\synplicity\\fpga_81\\lib\\vhd\\std.vhd":1111509844
#CUR:"D:\\synplicity\\fpga_81\\lib\\vhd\\std.vhd":1111509844
#CUR:"E:\\modelsim\\vr_fifo\\src\\vr_fifo_rtl.vhd":1154101091
#CUR:"E:\\modelsim\\vr_fifo\\src\\vr_fifo_rtl.vhd":1154101091
#CUR:"D:\\synplicity\\fpga_81\\lib\\vhd\\std1164.vhd":927285456
#CUR:"D:\\synplicity\\fpga_81\\lib\\vhd\\std1164.vhd":927285456
#CUR:"D:\\synplicity\\fpga_81\\lib\\vhd\\arith.vhd":1035356678
#CUR:"D:\\synplicity\\fpga_81\\lib\\vhd\\arith.vhd":1035356678
#CUR:"D:\\synplicity\\fpga_81\\lib\\vhd\\unsigned.vhd":1068614572
#CUR:"D:\\synplicity\\fpga_81\\lib\\vhd\\unsigned.vhd":1068614572
f "D:\synplicity\fpga_81\lib\vhd\std.vhd"; # file 0
af .is_vhdl 1;
f "E:\modelsim\vr_fifo\src\vr_fifo_rtl.vhd"; # file 1
af .is_vhdl 1;
f "D:\synplicity\fpga_81\lib\vhd\std1164.vhd"; # file 2
af .is_vhdl 1;
f "D:\synplicity\fpga_81\lib\vhd\arith.vhd"; # file 3
af .is_vhdl 1;
f "D:\synplicity\fpga_81\lib\vhd\unsigned.vhd"; # file 4
af .is_vhdl 1;
@E
@ 
ftell;
@E@MR@44:6::(446:dFRIsP	RsH_VVsFR0
D;N3PRHE#P84DR;P
NR#3H_8PED;R4
RNP3M#$_NVlbIR"FRs	\:" \F\l8#CDH\l\PVs_H\VF\O#s\s\P_VVHF0_sDE3P8
\""N;
PFR3shHoNRlC"_PsVFHV"
;

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;

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;

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R4@@:(4j:4c:j6(:RPHMR_HMsR8$HsM_8V$RH_VFVDkD;R
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b@:@44:.gc.:4gR:6HRMPk_M4P_D8b4Mr9MRk4D_P8M_brR49P_D8b4Mr9b;
Rj@@:44::.4:Rk0sCsR0k0CRs;kC
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";