verilog-A

CV181L-A-20_Specification_V1.0(大功放）

cv181l-a-20

标签： Specification_V 181 1.0 L-A

上传时间： 2013-10-20

上传用户：ikemada
宇闻着Verilog数字系统设计教程word版

宇闻着Verilog数字系统设计教程word版

标签： Verilog word 数字系统设计教程

上传时间： 2013-11-03

上传用户：zhang_yi
宇闻着Verilog数字系统设计教程word版

宇闻着Verilog数字系统设计教程word版

标签： Verilog word 数字系统设计教程

上传时间： 2013-10-11

上传用户：angle
《Verilog HDL程序设计与应用》

《Verilog HDL程序设计与实践》系统讲解了Verilog HDL的基本语法和高级应用技巧，对于每个知识点都按照开门见山、自顶向下的方式来组织内容，在介绍相关知识点之前，先告诉读者其出现的背景、本质特征以及应用场景，让读者不仅掌握基本语法，还能够获得深层次理解。从结构上讲，《Verilog HDL程序设计与实践》以Verilog HDL的各方面开发为主线，遵照硬件应用系统开发的基本步骤和思路进行详细讲解，并穿插介绍ISE开发工具的操作技巧与注意事项，具备很强的可读性、指导性和实用性。

标签： Verilog HDL 程序设计

上传时间： 2013-11-21

上传用户：silenthink
Employing a Single-Chip Transceiver in Femtocell Base-Station Applications

Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."

标签： Base-Station Applications Single-Chip Transceiver

上传时间： 2013-11-05

上传用户：超凡大师
夏宇闻Verilog经典教程

夏宇闻Verilog经典教程

标签： Verilog 教程

上传时间： 2013-10-21

上传用户：zhangyi99104144
XAPP143-利用Verilog来创建CPLD设计

This Application Note covers the basics of how to use Verilog as applied to ComplexProgrammable Logic Devices. Various combinational logic circuit examples, such asmultiplexers, decoders, encoders, comparators and adders are provided. Synchronous logiccircuit examples, such as counters and state machines are also provided.

标签： Verilog XAPP CPLD 143

上传时间： 2013-11-11

上传用户：y13567890
Verilog编码中的非阻塞性赋值

One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assignments should be used. This paper details how Verilog blocking andnonblocking assignments are scheduled, gives important coding guidelines to infer correctsynthesizable logic and details coding styles to avoid Verilog simulation race conditions

标签： Verilog 编码非阻塞性赋值

上传时间： 2013-11-01

上传用户：xzt
State Machine Coding Styles for Synthesis

本文论述了状态机的verilog编码风格,以及不同编码风格的优缺点，Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concerning the origin of specific state machine types.This paper, "State Machine Coding Styles for Synthesis," details additional insights into statemachine design including coding style approaches and a few additional tricks.

标签： Synthesis Machine Coding Styles

上传时间： 2013-10-12

上传用户：sardinescn
Design Safe Verilog State Machine（Synplicity）

One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability analysis to determine all the states that could possibly bereached, and optimize away all states and transition logic that can not be reached.Thus, producing a highly optimal final implementation of the state machine.

标签： Synplicity Machine Verilog Design

上传时间： 2013-10-20

上传用户：苍山观海