搜索：vHD - 虫虫下载站

VHDL/FPGA/Verilog 用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench

用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench

https://www.eeworm.com/dl/663/132718.html

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VHDL/FPGA/Verilog 本文件解压后clock_time.vhd采用编程环境maxplusII

本文件解压后clock_time.vhd采用编程环境maxplusII，完成时间秒定时、记时，设置时间秒、声光报警等功能。

https://www.eeworm.com/dl/663/139634.html

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VHDL/FPGA/Verilog 福州大学EDA选修课所有实验课程代码。VHDL语言描述（vhd）

福州大学EDA选修课所有实验课程代码。VHDL语言描述（vhd），以及电路图（gdf）

https://www.eeworm.com/dl/663/150153.html

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VHDL/FPGA/Verilog VHDL 关于2DFFT设计程序 u scinode1 &#8764 scinode9.vhd: Every SCI node RTL vhdl code. The details can be

VHDL 关于2DFFT设计程序 u scinode1 &#8764 scinode9.vhd: Every SCI node RTL vhdl code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus network, and it support these sub-modules scinode1&#8764 scinode9 reset and clk and glob ...

https://www.eeworm.com/dl/663/152303.html

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VHDL/FPGA/Verilog max+plusII下编成的直流电机控制器vhd

max+plusII下编成的直流电机控制器vhd

https://www.eeworm.com/dl/663/162460.html

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VHDL/FPGA/Verilog max+plusII下的各种功能的计数器vhd

max+plusII下的各种功能的计数器vhd

https://www.eeworm.com/dl/663/162472.html

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VHDL/FPGA/Verilog /* This program generates the DApkg.vhd file that is used to define * the DA filter core and give

/* This program generates the DApkg.vhd file that is used to define * the DA filter core and gives its parameters and the contents of the * Distributed Arithmetic Look-up-table "DALUT" according to the DA algorithm

https://www.eeworm.com/dl/663/172721.html

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VHDL/FPGA/Verilog <Floating Point Unit Core> fpupack.vhd pre_norm_addsub.vhd addsub_28.vhd post_norm_addsub.

<Floating Point Unit Core> fpupack.vhd pre_norm_addsub.vhd addsub_28.vhd post_norm_addsub.vhd pre_norm_mul.vhd mul_24.vhd vcom serial_mul.vhd post_norm_mul.vhd pre_norm_div.vhd serial_div.vhd post_norm_div.vhd pre_norm_sqrt.vhd sqrt.vhd post_norm_sqrt.vhd comppack.vhd fpu.vhd ***For simulation **** ...

https://www.eeworm.com/dl/663/172732.html

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VHDL/FPGA/Verilog 数字钟的vhd文档

数字钟的vhd文档，个人感觉还是蛮完善的，大家可以下载了一同改进。

https://www.eeworm.com/dl/663/183745.html

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VHDL/FPGA/Verilog fulladder.vhd 一位全加器 adder.vhd 四位全加器 multi4.vhd 四位并行乘法器

fulladder.vhd 一位全加器 adder.vhd 四位全加器 multi4.vhd 四位并行乘法器

https://www.eeworm.com/dl/663/192196.html

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