SDN （Software Defined Networking）作为当前最重要的热门技术之一，目前已经普遍得到大家的共识。有关SDN的资料和书籍非常丰富，但入门和学习SDN依然是非常困难。本书整理了SDN实践中的一些基本理论和实践案例心得，希望能给大家带来启发，也欢迎大家关注和贡献。本书内容包括网络基础SDN网络容器网络Linux网络OVS以及DPDKSD-WANNFV实践案例
上传时间： 2021-12-09
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基于FPGA设计的sdram读写测试实验Verilog逻辑源码Quartus工程文件+文档说明，DRAM选用海力士公司的 HY57V2562 型号,容量为的 256Mbit,采用了 54 引脚的TSOP 封装, 数据宽度都为 16 位, 工作电压为 3.3V,并丏采用同步接口方式所有的信号都是时钟信号。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
标签： fpga sdram verilog quartus
上传时间： 2021-12-18
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Xilinx FPGA Virtex-7 全系列（AD集成封装库），IntLib后缀文件，PCB封装带3D视图，拆分后文件为PcbLib+SchLib格式，Altium Designer原理图库+PCB封装库，集成封装型号列表：Library Component Count : 157Name Description----------------------------------------------------------------------------------------------------XC7V2000T-1FHG1761C Virtex-7 FPGA, 1200 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 1, Commerical Grade, Pb-FreeXC7V2000T-1FHG1761I Virtex-7 FPGA, 1200 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7V2000T-1FLG1925C Virtex-7 FPGA, 1200 User I/Os, 16 GTX, 1924-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7V2000T-1FLG1925I Virtex-7 FPGA, 1200 User I/Os, 16 GTX, 1924-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7V2000T-2FHG1761C Virtex-7 FPGA, 1200 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 2, Commerical Grade, Pb-FreeXC7V2000T-2FLG1925C Virtex-7 FPGA, 1200 User I/Os, 16 GTX, 1924-Ball BGA, Speed Grade 2, Commercial Grade, Pb-FreeXC7V2000T-2GFHG1761EVirtex-7 FPGA, 1200 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 2G, Extended Grade, Pb-FreeXC7V2000T-2GFLG1925EVirtex-7 FPGA, 1200 User I/Os, 16 GTX, 1924-Ball BGA, Speed Grade 2G, Extended Grade, Pb-FreeXC7V2000T-2LFHG1761EVirtex-7 FPGA, 1200 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 2L, Extended Grade, Pb-FreeXC7V2000T-2LFLG1925EVirtex-7 FPGA, 1200 User I/Os, 16 GTX, 1924-Ball BGA, Speed Grade 2L, Extended Grade, Pb-FreeXC7V585T-1FFG1157C Virtex-7 FPGA, 850 User I/Os, 20 GTX, 1156-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7V585T-1FFG1157I Virtex-7 FPGA, 850 User I/Os, 20 GTX, 1156-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7V585T-1FFG1761C Virtex-7 FPGA, 850 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7V585T-1FFG1761I Virtex-7 FPGA, 850 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7V585T-2FFG1157C Virtex-7 FPGA, 850 User I/Os, 20 GTX, 1156-Ball BGA, Speed Grade 2, Commercial Grade, Pb-FreeXC7V
上传时间： 2021-12-22
上传用户：aben
Xilinx FPGA Artix-7 全系列（AD集成封装库），IntLib后缀文件，PCB封装带3D视图，拆分后文件为PcbLib+SchLib格式，Altium Designer原理图库+PCB封装库，集成封装型号列表：Library Component Count : 48Name Description----------------------------------------------------------------------------------------------------XC7A100T-1CSG324C Artix-7 FPGA, 210 User I/Os, 0 GTP, 324-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7A100T-1CSG324I Artix-7 FPGA, 210 User I/Os, 0 GTP, 324-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7A100T-1FGG484C Artix-7 FPGA, 285 User I/Os, 4 GTP, 484-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7A100T-1FGG484I Artix-7 FPGA, 285 User I/Os, 4 GTP, 484-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7A100T-1FGG676C Artix-7 FPGA, 300 User I/Os, 8 GTP, 676-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7A100T-1FGG676I Artix-7 FPGA, 300 User I/Os, 8 GTP, 676-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7A100T-1FTG256C Artix-7 FPGA, 170 User I/Os, 0 GTP, 256-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7A100T-1FTG256I Artix-7 FPGA, 170 User I/Os, 0 GTP, 256-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7A100T-2CSG324C Artix-7 FPGA, 210 User I/Os, 0 GTP, 324-Ball BGA, Speed Grade 2, Commercial Grade, Pb-FreeXC7A100T-2CSG324I Artix-7 FPGA, 210 User I/Os, 0 GTP, 324-Ball BGA, Speed Grade 2, Industrial Grade, Pb-FreeXC7A100T-2FGG484C Artix-7 FPGA, 285 User I/Os, 4 GTP, 484-Ball BGA, Speed Grade 2, Commercial Grade, Pb-FreeXC7A100T-2FGG484I Artix-7 FPGA, 285 User I/Os, 4 GTP, 484-Ball BGA, Speed Grade 2, Industrial Grade, Pb-FreeXC7A100T-2FGG676C Artix-7 FPGA, 300 User I/Os, 8 GTP, 676-Ball BGA, Speed Grade 2, Commercial Grade, Pb-FreeXC7A100T-2FGG676I Artix-7 FPGA, 300 User I/Os, 8 GTP, 676-Ball BGA, Speed Grade 2, Industrial Grade, Pb-FreeXC7A100T-2FTG256C Artix-7 FPGA, 170 User I/Os, 0 GTP, 256-Ball BGA, Speed Grade 2, Commercial Grade, Pb-FreeXC7A100T-2FTG256I Artix-7 FPGA, 170 User I/Os, 0 GTP, 2
上传时间： 2021-12-22
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5G中的SDN-NFV和云计算.pdf摘 要 通过介绍广义的SDN/NFV和云计算，结合未来5G网络的特点，分析了5G中上述技术的 应用前景和技术定位；结合5G的网络特点和现有网络的部署情况，总结了各技术间的逻辑关系以及运 营商的侧重点。引言 SDN/NFV 和云计算都是起源于 IT 领域的技术。 如今，云计算已经非常成熟，在 IT 领域已经大规模商 用，SDN技术作为新兴的转发技术，也已经被谷歌等互 联网巨头部署在多个数据中心。随着虚 拟化技术的发展，人们试图将更多的专有 设备虚拟化和软件化，从而达到降低成本 和灵活部署的目的，于是 NFV 的概念诞 生了。本文将结合广义上 3 种技术本身 的特点和未来5G的网络能力要求，分析 各技术在5G架构中的技术定位和前景， 同时结合实际的发展情况，总结未来运营 商在技术研发和业务模式上的侧重点。 1.1 广义的SDN及标准化进程 ONF 在 2012 年 4 月 发 布 白 皮 书 《Software- Defined Networking: The New Norm for Networks》
标签： 5G
上传时间： 2022-02-25
上传用户：jason_vip1
本文主要介绍如何在Wado设计套件中进行时序约束，原文出自 xilinx中文社区。1 Timing Constraints in Vivado-UCF to xdcVivado软件相比于sE的一大转变就是约束文件，5E软件支持的是UcF（User Constraints file，而 Vivado软件转换到了XDc（Xilinx Design Constraints）。XDC主要基于SDc（Synopsys Design Constraints）标准，另外集成了Xinx的一些约束标准可以说这一转变是xinx向业界标准的靠拢。Altera从 TimeQuest开始就一直使用SDc标准，这一改变，相信对于很多工程师来说是好事，两个平台之间的转换会更加容易些。首先看一下业界标准SDc的原文介绍：Synopsys widely-used design constraints format, known as sDc, describes the design intent"and surrounding constraints for synthesis, clocking, timing, power, test and environmental and operating conditions. sDc has been in use and evolving for more than 20 years, making it the most popular and proven format for describing design constraints. Essentially all synthesized designs use SDc and numerous EDa companies have translators that can read and process sDc
标签： vivado
上传时间： 2022-03-26
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Allegro导出 Gerber文件和钻孔数据文件很多PCB厂家都没有装Allegro软件，所以你不能直接发.brd文件。（很多PCB小厂连ProtelDXP也没有，只支持Protel99）什么是Gerber文件Gerber文件是所有电路设计软件都可以产生的文件，在电子组装行业又称为模版文件（stencil data），在PCB制造业又称为光绘文件。可以说Gerber文件是电子组装业中最通用最广泛的文件格式Gerber文件是EIA的标准格式，分RS274-D和RS274-X两种，其中RS274-X是RS274-D的扩展文件。生产制造部门在条件许可的情况下，应当尽可能要求用户或设计部门提供RS274-X的Gerber文件，这样有利于各工序的生产准备。准备工作为了保证出片的正确性，需要在设计PCB文件之前对一些系统参数进行设置，该设置包括画图的精度，图片的尺寸，动态铺铜的格式。设置画图的精度。在allegro中打开Setup->Drawing Size菜单，调出设置对话框，如图1在对话框中确定User Units选择Mils，Size选择C，这样整个作图区域会大一点，相应的作图范围（Drawing Extents）变为Width：22000.00：Height：17000.00Left X和LeftY为原点坐标。Accuracy选择2，其他根据你的尺寸自行定义。设置完成选择OK按钮，使配置生效。
上传时间： 2022-04-30
上传用户：zhaiyawei
This manual documents the Microcontroller profile of version 7 of the ARM® Architecture, the ARMv7-M architecture profile. For short definitions of all the ARMv7 profiles see About the ARMv7 architecture, and architecture profiles on page A1-20.ARMv7 is documented as a set of architecture profiles. The profiles are defined as follows: ARMv7-A The application profile for systems supporting the ARM and Thumb instruction sets, and requiring virtual address support in the memory management model. ARMv7-R The realtime profile for systems supporting the ARM and Thumb instruction sets, and requiring physical address only support in the memory management model ARMv7-M The microcontroller profile for systems supporting only the Thumb instruction set, and where overall size and deterministic operation for an implementation are more important than absolute performance. While profiles were formally introduced with the ARMv7 development, the A-profile and R-profile have implicitly existed in earlier versions, associated with the Virtual Memory System Architecture (VMSA) and Protected Memory System Architecture (PMSA) respectively.
标签： arm
上传时间： 2022-06-02
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ICN6201/02 is a bridge chip which receives MIPI® DSI inputs and sends LVDS outputs. MIPI® DSI supports up to 4 lanes and each lane operates at 1Gbps maximum; the totally maximum input bandwidth is 4Gbps; and the MIPI defined ULPS(ultra-low-power state) is also supported. ICN6201 decodes MIPI® DSI 18bepp RGB666 and 24bpp RGB888 packets.The LVDS output 18 or 24 bits pixel with 25MHz to 154MHz, by VESA or JEIDA format.ICN6201/02 support video resolution up to FHD (1920x1080) and WUXGA (1920x1200).ICN6201 adopts QFN48 package and ICN6202 adopts QFN40 package
标签： icn6202
上传时间： 2022-06-10
上传用户：kingwide
Mathematical modeling has become an important part of the research and devclopment work in engineering and scicnce. Retaining a competitive edge requiresa fast path between ideas and prototypes, and in this regard mathematical modeling and simulation provide a valuable shortcut for understanding both qualitative and quantitative aspects of scientific and engineering design. To assist you in gaining this edge, COMSOL Multiphysics offers state-of-the art performance, being built from the ground up with a Java3D interface and C/C++ solvers.The Acoustics Module is an optional package that extends the COMSOL Multiphysicsmodcling cnvironment with customized user interfaces and functionality optimizcd for the analysis of acoustics. Like all modules in the COMSOL family, it provides a brary of prewritten ready-to-run models that make it quicker and casier to analyze disciplinc-specific problcms.
上传时间： 2022-06-19
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