VHDL code for a clock divider by 27 circuit with a resulting waveform with 50% duty cycle..
VHDL code for a clock divider by 27 circuit with a resulting waveform with 50% duty cycle..
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VHDL code for a clock divider by 27 circuit with a resulting waveform with 50% duty cycle..
This code is described in "Computational Geometry in C" (Second Edition), Chapter 8. It is not written to be comprehens...
Nucleus PLUS source code anasisy. An open source OS which is widely used in embedded development domain.
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Implementation for Lempel-Ziv code. Encoder and decoder are separated. The input is a file and the output is written ...
Contains code for freertos port to AT91SAM7X512.Anybody can use these codes for non commercial use only.
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This delphi 7 source code have a function to send SMS trough computer with serial communication. You can modify it for y...