Integrated EMI/Thermal Design forSwitching Power SuppliesWei ZhangThesis submitted to the Faculty of theVirginia Polytechnic Institute and State Universityin partial fulfillment of the requirements for the degree of Integrated EMI/Thermal Design forSwitching Power SuppliesWei Zhang(ABSTRACT)This work presents the modeling and analysis of EMI and thermal performancefor switch power supply by using the CAD tools. The methodology and design guidelinesare developed.By using a boost PFC circuit as an example, an equivalent circuit model is builtfor EMI noise prediction and analysis. The parasitic elements of circuit layout andcomponents are extracted analytically or by using CAD tools. Based on the model, circuitlayout and magnetic component design are modified to minimize circuit EMI. EMI filtercan be designed at an early stage without prototype implementation.In the second part, thermal analyses are conducted for the circuit by using thesoftware Flotherm, which includes the mechanism of conduction, convection andradiation. Thermal models are built for the components. Thermal performance of thecircuit and the temperature profile of components are predicted. Improved thermalmanagement and winding arrangement are investigated to reduce temperature.In the third part, several circuit layouts and inductor design examples are checkedfrom both the EMI and thermal point of view. Insightful information is obtained.
上传时间： 2013-11-16
上传用户：萍水相逢
解压密码：www.elecfans.com 随着微电子技术的迅速发展以及集成电路规模不断提高，对电路性能的设计 要求越来越严格，这势必对用于大规模集成电路设计的EDA 工具提出越来越高的 要求。自1972 年美国加利福尼亚大学柏克莱分校电机工程和计算机科学系开发 的用于集成电路性能分析的电路模拟程序SPICE（Simulation Program with IC Emphasis）诞生以来，为适应现代微电子工业的发展，各种用于集成电路设计的 电路模拟分析工具不断涌现。HSPICE 是Meta-Software 公司为集成电路设计中 的稳态分析，瞬态分析和频域分析等电路性能的模拟分析而开发的一个商业化通 用电路模拟程序，它在柏克莱的SPICE（1972 年推出），MicroSim公司的PSPICE （1984 年推出）以及其它电路分析软件的基础上，又加入了一些新的功能，经 过不断的改进，目前已被许多公司、大学和研究开发机构广泛应用。HSPICE 可 与许多主要的EDA 设计工具，诸如Candence,Workview 等兼容，能提供许多重要 的针对集成电路性能的电路仿真和设计结果。采用HSPICE 软件可以在直流到高 于100MHz 的微波频率范围内对电路作精确的仿真、分析和优化。在实际应用中， HSPICE能提供关键性的电路模拟和设计方案，并且应用HSPICE进行电路模拟时， 其电路规模仅取决于用户计算机的实际存储器容量。 The HSPICE Integrator Program enables qualified EDA vendors to integrate their products with the de facto standard HSPICE simulator, HSPICE RF simulator, and WaveView Analyzer™. In addition, qualified HSPICE Integrator Program members have access to HSPICE integrator application programming interfaces (APIs). Collaboration between HSPICE Integrator Program members will enable customers to achieve more thorough design verification in a shorter period of time from the improvements offered by inter-company EDA design solutions.
上传时间： 2013-10-18
上传用户：s363994250
PCB设计问题集锦 问：PCB图中各种字符往往容易叠加在一起，或者相距很近，当板子布得很密时，情况更加严重。当我用Verify Design进行检查时，会产生错误，但这种错误可以忽略。往往这种错误很多，有几百个，将其他更重要的错误淹没了，如何使Verify Design会略掉这种错误，或者在众多的错误中快速找到重要的错误。 答：可以在颜色显示中将文字去掉,不显示后再检查;并记录错误数目。但一定要检查是否真正属于不需要的文字。 问： What’s mean of below warning:(6230,8330 L1) Latium Rule not checked: COMPONENT U26 component rule.答：这是有关制造方面的一个检查，您没有相关设定，所以可以不检查。 问： 怎样导出jop文件？答：应该是JOB文件吧？低版本的powerPCB与PADS使用JOB文件。现在只能输出ASC文件，方法如下STEP：FILE/EXPORT/选择一个asc名称/选择Select ALL/在Format下选择合适的版本/在Unit下选Current比较好/点击OK/完成然后在低版本的powerPCB与PADS产品中Import保存的ASC文件，再保存为JOB文件。 问： 怎样导入reu文件？答：在ECO与Design 工具盒中都可以进行，分别打开ECO与Design 工具盒，点击右边第2个图标就可以。 问： 为什么我在pad stacks中再设一个via:1(如附件）和默认的standardvi(如附件）在布线时V选择1，怎么布线时按add via不能添加进去这是怎么回事，因为有时要使用两种不同的过孔。答：PowerPCB中有多个VIA时需要在Design Rule下根据信号分别设置VIA的使用条件，如电源类只能用Standard VIA等等，这样操作时就比较方便。详细设置方法在PowerPCB软件通中有介绍。 问：为什么我把On-line DRC设置为prevent..移动元时就会弹出(图2),而你们教程中也是这样设置怎么不会呢?答：首先这不是错误,出现的原因是在数据中没有BOARD OUTLINE.您可以设置一个,但是不使用它作为CAM输出数据. 问：我用ctrl+c复制线时怎设置原点进行复制，ctrl+v粘帖时总是以最下面一点和最左边那一点为原点 答： 复制布线时与上面的MOVE MODE设置没有任何关系,需要在右键菜单中选择,这在PowerPCB软件通教程中有专门介绍. 问：用(图4)进行修改线时拉起时怎总是往左边拉起(图5)，不知有什么办法可以轻易想拉起左就左，右就右。答： 具体条件不明,请检查一下您的DESIGN GRID,是否太大了. 问： 好不容易拉起右边但是用(图6)修改线怎么改怎么下面都会有一条不能和在一起，而你教程里都会好好的(图8)答：这可能还是与您的GRID 设置有关,不过没有问题,您可以将不需要的那段线删除.最重要的是需要找到布线的感觉,每个软件都不相同,所以需要多练习。 问： 尊敬的老师:您好！这个图已经画好了，但我只对（如图1）一种的完全间距进行检查，怎么错误就那么多，不知怎么改进。请老师指点。这个图在附件中请老师帮看一下，如果还有什么问题请指出来，本人在改进。谢！！！！！答：请注意您的DRC SETUP窗口下的设置是错误的,现在选中的SAME NET是对相同NET进行检查,应该选择NET TO ALL.而不是SAME NET有关各项参数的含义请仔细阅读第5部教程. 问： U101元件已建好，但元件框的拐角处不知是否正确，请帮忙CHECK 答：元件框等可以通过修改编辑来完成。问： U102和U103元件没建完全，在自动建元件参数中有几个不明白：如：SOIC--》silk screen栏下spacing from pin与outdent from first pin对应U102和U103元件应写什么数值，还有这两个元件SILK怎么自动设置，以及SILK内有个圆圈怎么才能画得与该元件参数一致。 答：Spacing from pin指从PIN到SILK的Y方向的距离,outdent from first pin是第一PIN与SILK端点间的距离.请根据元件资料自己计算。
上传时间： 2014-01-03
上传用户：Divine
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上传时间： 2014-01-24
上传用户：s363994250
Abstract: This application note presents an overview of electronic margining and its value in detectingpotential system failures before a product ships from the factory. It is a calibration method that effectivelypredicts and allows adjustments to improve product quality. Margining also can be used to sort productsinto performance levels, allowing premium products to be sold at premium prices. We discuss thedownside of sorting and suggest alternative ways to segregate products.
上传时间： 2014-01-22
上传用户：lhw888
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
上传时间： 2013-12-25
上传用户：jkhjkh1982
The high defi nition multimedia interface (HDMI) is fastbecoming the de facto standard for passing digitalaudio and video data in home entertainment systems.This standard includes an I2C type bus called a displaydata channel (DDC) that is used to pass extended digitalinterface data (EDID) from the sinkdevice (such as adigital TV) to the source device (such as a digital A/Vreceiver). EDID includes vital information on the digitaldata formats that the sink device can accept. The HDMIspecifi cation requires that devices have less than 50pFof input capacitance on their DDC bus lines, which canbe very diffi cult to meet. The LTC®4300A’s capacitancebuffering feature allows devices to pass the HDMI DDCinput capacitance compliance test with ease.
上传时间： 2013-11-21
上传用户：tian126vip
ACPR (adjacent channel power ratio), AltCPR (alternatechannel power ratio), and noise are important performancemetrics for digital communication systems thatuse, for example, WCDMA (wideband code division multipleaccess) modulation. ACPR and AltCPR are bothmeasures of spectral regrowth. The power in the WCDMAcarrier is measured using a 5MHz measurement bandwidth;see Figure 1. In the case of ACPR, the total powerin a 3.84MHz bandwidth centered at 5MHz (the carrierspacing) away from the center of the outermost carrier ismeasured and compared to the carrier power. The resultis expressed in dBc. For AltCPR, the procedure is thesame, except we center the measurement 10MHz awayfrom the center of the outermost carrier.
上传时间： 2013-11-02
上传用户：maricle
USB TO RS232 RS485 UART转接板电路原理图
上传时间： 2013-10-22
上传用户：macarco
program to trasmit data to a TI92 with the TI Graph-Link
标签： Graph-Link program trasmit data
上传时间： 2015-01-03
上传用户：youke111
