this is the vhdl code of arithmetic and logic unit of 16 bit microprocessor.
标签： microprocessor arithmetic logic this
上传时间： 2013-12-07
上传用户：jcljkh
This book deals with the VHDL programming with synthesible examples...good for begineers
标签： with programming synthesible begineers
上传时间： 2014-01-01
上传用户：cuiyashuo
Clock based on the VHDL design language, the revised time alarm can be set up
标签： the language revised design
上传时间： 2013-12-09
上传用户：haoxiyizhong
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
上传时间： 2014-12-23
上传用户：xinhaoshan2016
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
上传时间： 2013-11-20
上传用户：pzw421125
-- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn
标签： entity-architectures Multiplier contains complete
上传时间： 2015-07-02
上传用户：2467478207
关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
标签： investigates implementing pipelines circuits
上传时间： 2015-07-26
上传用户：CHINA526
-- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check
标签： entity-architectures Multiplier contains complete
上传时间： 2014-01-22
上传用户：lijianyu172
This document accompanies a sample co-installer that can be used in conjunction with an INF file to install additional device INF files on the target system during a device installation. The instructions herein apply to the Microsoft Windows 2000 and Windows XP and Windows Server 2003 operating systems. The sample co-installer described in this article interprets CopyINF directives in a [DDInstall] section in an INF file. The sample demonstrates using a co-installer to perform processing after a device has been installed, parsing the INF section that is being used for the installation, and the use of the SetupCopyOEMInf, SetupGetInfInformation, SetupQueryInfOriginalFileInformation and SetupDiGetActualSectionToInstall APIs.
标签： co-installer accompanies conjunction document
上传时间： 2014-02-28
上传用户：gououo
摘要：本文主要介绍以CPLD 芯片进行十字路口的交通灯的设计，用CPLD 作为交通灯控制器的主控芯片，采用VHDL\r\n语言编写控制程序，利用CPLD的可重复编程和在动态系统重构的特性，大大地提高了数字系统设计的灵活性和通用性。\r\n关键词：CPLD；VHDL；交通灯控制器\r\n中图分类号：TP39\r\nAbstract ：This paper introduces the electronic-traffic lamp, which is based on the VHDL and is com
上传时间： 2013-08-11
上传用户：aesuser
