This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
上传时间： 2014-12-23
上传用户：xinhaoshan2016
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
上传时间： 2013-11-20
上传用户：pzw421125
数字运算，判断一个数是否接近素数 A Niven number is a number such that the sum of its digits divides itself. For example, 111 is a Niven number because the sum of its digits is 3, which divides 111. We can also specify a number in another base b, and a number in base b is a Niven number if the sum of its digits divides its value. Given b (2 <= b <= 10) and a number in base b, determine whether it is a Niven number or not. Input Each line of input contains the base b, followed by a string of digits representing a positive integer in that base. There are no leading zeroes. The input is terminated by a line consisting of 0 alone. Output For each case, print "yes" on a line if the given number is a Niven number, and "no" otherwise. Sample Input 10 111 2 110 10 123 6 1000 8 2314 0 Sample Output yes yes no yes no
上传时间： 2015-05-21
上传用户：daguda
-- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn
标签： entity-architectures Multiplier contains complete
上传时间： 2015-07-02
上传用户：2467478207
关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
标签： investigates implementing pipelines circuits
上传时间： 2015-07-26
上传用户：CHINA526
-- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check
标签： entity-architectures Multiplier contains complete
上传时间： 2014-01-22
上传用户：lijianyu172
We have a group of N items (represented by integers from 1 to N), and we know that there is some total order defined for these items. You may assume that no two elements will be equal (for all a, b: a<b or b<a). However, it is expensive to compare two items. Your task is to make a number of comparisons, and then output the sorted order. The cost of determining if a < b is given by the bth integer of element a of costs (space delimited), which is the same as the ath integer of element b. Naturally, you will be judged on the total cost of the comparisons you make before outputting the sorted order. If your order is incorrect, you will receive a 0. Otherwise, your score will be opt/cost, where opt is the best cost anyone has achieved and cost is the total cost of the comparisons you make (so your score for a test case will be between 0 and 1). Your score for the problem will simply be the sum of your scores for the individual test cases.
标签： represented integers group items
上传时间： 2016-01-17
上传用户：jeffery
Generate 100 samples of a zero-mean white noise sequence with variance , by using a uniform random number generator. a Compute the autocorrelation of for . b Compute the periodogram estimate and plot it. c Generate 10 different realizations of , and compute the corresponding sample autocorrelation sequences , and . Compute the average autocorrelation sequence as and the corresponding periodogram for . d Compute and plot the average periodogram using the Bartlett method. e Comment on the results in parts (a) through (d).
标签： zero-mean Generate sequence variance
上传时间： 2016-03-04
上传用户：朗朗乾坤
PARALLEL PORT JTAG PROGRAMMER Adaptor used to program the S3C2410 samsung processor. The rar file contains PDF and DSN format circuit diagram. This can be used and to make your own parallel port wiggler programmer
标签： PROGRAMMER processor PARALLEL Adaptor
上传时间： 2013-12-05
上传用户：zhangzhenyu
boost的matlab代码， Matlab source codes for the Boosting of the J-DLDA learner(B-JDLDA)
标签： boostcode
上传时间： 2015-03-23
上传用户：52086
