usb_cpld_code.zip usbjtag - Variations on the implementation of a USB JTAG adapter.
标签： implementation usb_cpld_code Variations adapter
上传时间： 2013-08-31
上传用户：ruan2570406
something useful for communication,source code based on FPGA
标签： communication something useful source
上传时间： 2013-08-31
上传用户：maizezhen
On the design of an FPGA-Based OFDM modulator for IEEE 802.11a
标签： FPGA-Based modulator 802.11 design
上传时间： 2013-09-02
上传用户：zjwangyichao
The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and implement DSP algorithms targeting FPGAs. This intermediate workshop in implementing DSP functions focuses on learning how to use System Generator for DSP,
标签： workshop provides Design Flow
上传时间： 2013-09-02
上传用户：joheace
Building a RISC System in an FPGA
上传时间： 2013-09-04
上传用户：朗朗乾坤
本设计的基本要求是以复杂可编程逻辑器件CPLD为基础，通过在EDA系统软件ispDesignExpert System 环境下进行数字系统设计，熟练掌握该环境下的功能仿真，时间仿真，管脚锁定和芯片下载。 本系统基本上比较全面的模拟了计数式数字频率计，广泛应用于工业、民用等各个领域，具有一定的开发价值。
标签： ispDesignExpert System EDA 系统软件
上传时间： 2013-09-05
上传用户：文993
System will automatically delete the directory
标签： automatically directory System delete
上传时间： 2013-09-09
上传用户：toyoad
protel s help on line
上传时间： 2013-09-18
上传用户：iswlkje
本文简单讨论并总结了VHDL、Verilog，System verilog 这三中语言的各自特点和区别As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
标签： Verilog verilog System VHDL
上传时间： 2013-10-16
上传用户：牛布牛
Introduce High-Speed Digital System Design.
标签： High-Speed Digital Design System
上传时间： 2013-10-20
上传用户：gps6888
