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style

  • This is style Swither

    This is style Swither

    标签: Swither style This is

    上传时间: 2017-06-05

    上传用户:GavinNeko

  • CSS 是 Cascading style Sheet 的缩写。译作「层叠样式表单」。是用于(增强)控制网页样式并允许将样式信息与网页内容分离的一种标记性语言,全面介绍CSS

    CSS 是 Cascading style Sheet 的缩写。译作「层叠样式表单」。是用于(增强)控制网页样式并允许将样式信息与网页内容分离的一种标记性语言,全面介绍CSS,还有一些实例

    标签: CSS Cascading style Sheet

    上传时间: 2013-12-15

    上传用户:思琦琦

  • C Cpp Programming style Guidlines

    C Cpp Programming style Guidlines

    标签: Programming Guidlines style Cpp

    上传时间: 2017-06-30

    上传用户:小眼睛LSL

  • H=CIRCLE(CENTER,RADIUS,NOP,style) This routine draws a circle with center defined as a vector

    H=CIRCLE(CENTER,RADIUS,NOP,style) This routine draws a circle with center defined as a vector CENTER, radius as a scaler RADIS. NOP is the number of points on the circle. As to style, use it the same way as you use the rountine PLOT. Since the handle of the object is returned, you use routine SET to get the best result.

    标签: routine defined CIRCLE CENTER

    上传时间: 2014-12-07

    上传用户:as275944189

  • XPMenu is a Delphi component to mimic Office XP menu and toolbar style. Copyright (C) 2001 Khaled S

    XPMenu is a Delphi component to mimic Office XP menu and toolbar style. Copyright (C) 2001 Khaled Shagrouni.

    标签: Copyright component toolbar XPMenu

    上传时间: 2013-12-30

    上传用户:古谷仁美

  • 电子书-RTL Design style Guide for Verilog HDL540页

    电子书-RTL Design style Guide for Verilog HDL540页A FF having a fixed input value is generated from the description in the upper portion of Example 2-21. In this case, ’0’ is output when the reset signal is asynchronously input, and ’1’ is output when the START signal rises. Therefore, the FF data input is fixed at the power supply, since the typical value ’1’ is output following the rise of the START signal. When FF input values are fixed, the fixed inputs become untestable and the fault detection rate drops. When implementing a scan design and converting to a scan FF, the scan may not be executed properl not be executed properly, so such descriptions , so such descriptions are not are not recommended. recommended.[1] As in the lower part of Example 2-21, be sure to construct a synchronous type of circuit and ensure that the clock signal is input to the clock pin of the FF. Other than the sample shown in Example 2-21, there are situations where for certain control signals, those that had been switched due to the conditions of an external input will no longer need to be switched, leaving only a FF. If logic exists in a lower level and a fixed value is input from an upper level, the input value of the FF may also end up being fixed as the result of optimization with logic synthesis tools. In a situation like this, while perhaps difficult to completely eliminate, the problem should be avoided as much as possible.

    标签: RTL verilog hdl

    上传时间: 2022-03-21

    上传用户:canderile

  • Verilog Coding style for Efficient Digital Design

      In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.

    标签: Efficient Verilog Digital Coding

    上传时间: 2013-11-22

    上传用户:han_zh

  • State Machine Coding styles for Synthesis

      本文论述了状态机的verilog编码风格,以及不同编码风格的优缺点,Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concerning the origin of specific state machine types.This paper, "State Machine Coding styles for Synthesis," details additional insights into statemachine design including coding style approaches and a few additional tricks.

    标签: Synthesis Machine Coding styles

    上传时间: 2013-10-15

    上传用户:dancnc

  • PCB覆铜高级连接方式

    在AD PCB 环境下,Design>Rules>Plane> Polygon Connect style ,点中Polygon Connect style,右键点击new rule ---新建一个规则点击新建的规则既选中该规则,在name 框中改变里面的内容即可修改该规则的名称,默认是PolygonConnect_1 ,现我们修改为GND-Via.

    标签: PCB 覆铜 连接方式

    上传时间: 2013-10-29

    上传用户:yunfan1978

  • 基于msp430单片机的便携式数字倾角仪的研制

    介绍了一种基于MSP430系列单片机和ADXL203加速度传感器的数字式倾角仪,它不仅可以实现水平度检测,而且可以测量00~3600范围内的任意倾角,分辨率可达O.1。。此外,由于该倾角仪输出为数字结果,因此它也可以与其他的数字设备结合起来,组合成一个功能更加强大的仪器。该数字倾角仪可广泛应用于建筑、机械、道路、桥梁、石油、煤矿和地质勘探等各种需要测量重力参考系下倾角的场合。关键词:MSP430F133单片机;力敏传感器;ADXL203加速度计;角度测量 Abstract:This paper presents a new style digital inclinometer which is developed on the basis of the MSP430F133 MCU and the ADXL203 dual axis aeeelerometer.This inclinometer not only can test levelness,but also can measure any angle between 0。and 360。with an accuracy of 0.1 O.In addition,its output is a digital result,which makes it possible to integrate itself with other digital devices to form a more functional unit.This inclinometer can be widely used in any construction site,oil field,coal-mine or geologic survey and SO on where it will provide the working people with convenience to measure any angles.Key words:MSP430F133 MCU;force sensor;ADXL203 accelerometer;angle measurement

    标签: msp 430 单片机 便携式

    上传时间: 2013-11-14

    上传用户:lizhizheng88