搜索：serdes
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设计相关
High Speed Serdes Design and Connectors
HIGH SPeed serdes designs and connectors and simulation models simulations used in signal Integrity and also has practical evaluation aof all connectors
https://www.eeworm.com/dl/838743.html
技术资料
FPGA的SERDES接口设计与实现
基于FPGA的SERDES接口设计与实现
https://www.eeworm.com/dl/837633.html
技术资料
高速串行SERDES以及应用介绍
SERDES是英文SERializer(串行器)/DESerializer(解串器)的简称。它是一种时分多路复用(TDM)、点对点的通信技术，即在发送端多路低速并行信号被转换成高速串行信号，经过传输媒体(光缆或铜线)，最后在接收端高速串行信号重新转换成低速并行信号。这种点对点的串行通信技术充分利用传输媒体的信道容量，减 ...
https://www.eeworm.com/dl/502/29069.html
单片机编程
MAXX9257 MAX9258芯片可编程SerDes持续时间计算
The MAX9257/MAX9258 programmable serializer/deserializer (SerDes) devices transfer both video data and control signals over the same twisted-pair cable. However, control data can only be transmitted during the vertical blank time, which is indicated by the control-channel-enabl ...
https://www.eeworm.com/dl/837634.html
技术资料
高速串行Serdes信号的眼图抖动测试
随着新研发单板上高速Serdes信号的增多，信号完整性测试显的越来越重要，本文档围绕Serdes信号的眼图抖动测试总结一些测试注意事项。新研发单板上高速Serdes信号速率高达2.45G，一些时钟信号上升/下降沿达到400ps左右，必然需要测量Serdes信号的眼图、抖动，在这里总结一些测试经验和注意事项。UBPG1单 ...
https://www.eeworm.com/dl/859847.html
技术资料
如何使用 HyperLynx DRC 来查找 SERDES 设计问题
如何使用 HyperLynx DRC 来查找 SERDES 设计问题
https://www.eeworm.com/dl/564/33745.html
通信网络
带有SerDes接口的PLB千兆位级以太网MAC
This application note describes a reference system which illustrates how to build an embeddedPowerPC® system using the Xilinx 1-Gigabit Ethernet Media Access Controller processor core.This system has the PLB_Gemac configured to use Scatter/Gather Direct Memory Access andthe ...