源码文件
-- Quad D-Type Flip-flop -- This example shows how a conditional signal assignment statement could be used to describe sequential…
sequential+logic 源代码
汇集 sequential+logic 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
收录资源 500 份
全站深度检索
共匹配 500 份工程资源
· 第 40 / 50 页
源码文件
//########################################################################### // // FILE: ADCcalibrationDriver.h // // TITLE: …
源码文件
//-< TESTPAR.CPP >---------------------------------------------------*--------* // FastDB Version 1.0 …
源码文件
-- Quad D-Type Flip-flop -- This example shows how a conditional signal assignment statement could be used to describe sequential…
源码文件
#include #include #include #include int a[10000]; /* array ini…
源码文件
-- Quad D-Type Flip-flop -- This example shows how a conditional signal assignment statement could be used to describe sequential…
源码文件
%CTRANSPOSE Transpose mapping (sequential or affine) % % W = CTRANSPOSE(W) % W = W' % % INPUT % W Mapping % % OUTPUT % W …
源码文件
#include "db.h" /* Return the next sequential record. * We just step our way through the index file, ignoring deleted * records…
源码文件
Information: Updating design information... (UID-85) **************************************** Report : area Design : Phone Versi…
源码文件
@N: CD630 :"D:\cpld\fpga\getpcm\baudr.vhd":5:7:5:11|Synthesizing work.baudr.art_baudr Post processing for work.baudr.art_baudr …