Precise interprocedural dataflow analysis via graph reachability
标签: interprocedural reachability dataflow analysis
上传时间: 2017-08-21
上传用户:trepb001
One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability analysis to determine all the states that could possibly bereached, and optimize away all states and transition logic that can not be reached.Thus, producing a highly optimal final implementation of the state machine.
标签: Synplicity Machine Verilog Design
上传时间: 2013-10-23
上传用户:司令部正军级
One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability analysis to determine all the states that could possibly bereached, and optimize away all states and transition logic that can not be reached.Thus, producing a highly optimal final implementation of the state machine.
标签: Synplicity Machine Verilog Design
上传时间: 2013-10-20
上传用户:苍山观海