c pre preocessor directive for debug messages and queue data structure implementation in c++.
标签： implementation preocessor directive structure
上传时间： 2013-12-15
上传用户：sy_jiadeyi
len tak pre radost len tak pre radost len tak pre radost len tak pre radost len tak pre radost
上传时间： 2017-07-15
上传用户：蠢蠢66
In higher power applications to utilize the full line power and reduce line currentharmonics
标签： Pre-Regulator Interleaved Design Review
上传时间： 2013-06-04
上传用户：lepoke
在无线通信系统全面进入3G并开始迈向 4G的过程中，使用数字预失真技术（Digital Pre-distortion，以下简称DPD）对发射机的功放进行线性化是一门关键技术。功率放大器是通信系统中影响系统性能和覆盖范围的关键部件，非线性是功放的固有特性。非线性会引起频谱增长(spectral re-growth)，从而造成邻道干扰，使带外杂散达不到协议标准规定的要求。非线性也会造成带内失真，带来系统误码率增大的问题。
上传时间： 2013-10-19
上传用户：yy_cn
两节锂电充电IC-ASC8512 ASC8512 为开关型两节锂聚合物电池充电管理芯片，非常适合于便携式设备的充电管理应用。ASC8512 集内置功率MOSFET、高精度电压和电流调节器、预充、充电状态指示和充电截止等功能于一体，采用TSSOP-14、SSOP-14两种封装形式。ASC8512对电池充电分为三个阶段：预充（Pre-charge）、恒流（CC／Constant Current）、恒压（CV／Constant Voltage）过程，恒流充电电流通过外部电阻决定，最大充电电流为2A.ASC8512 集成电流限制、短路保护，确保充电芯片安全工作。ASC8512 集成NTC 热敏电阻接口，可以采集、处理电池的温度信息，保证充电电池的安全工作温度。 两节锂电池充电IC ASC8512特点： 1.充2节锂离子和锂聚合物电池 2.开关频率达400K 3.充电电流最大可做2A 4.输入电压9V到18V 5.电池状态检测 6.恒压充电电压值可通过外接电阻微调 7.千分之五的充电电压控制精度 5.防反向保护电路可防止电池电流倒灌 6.NTC 热敏接口监测电池温度 7.LED充电状态指示 8.工作环境温度范围：-20℃～70℃ 9.TSSOP-14 应用领域：应用 ●手持设备，包括医疗手持设备 ●Portable-DVD，PDA，移动蜂窝电话及智能手机 ●上网本、平板电脑、MID ●自充电电池组
上传时间： 2013-11-06
上传用户：chfanjiang
Demonstration circuit 1562A is an engineering toolto design and evaluate the LTC699X-X family ofTimerBlox circuits. The center section of the boardcontains a pre-configured TimerBlox function.DC1562A comes in twelve timing function variationsas outlined in Table 1.Surrounding the center board is a ”playground”prototyping area. The prototyping area has padsfor Dip-8, S8, MS8, or S6 packages with breadboarding connections to each pin and two convenientpower buses and ground bus surrounding theentire area. This area is for conditioning signals tocontrol the timer function and for adding loads controlled in time.
上传时间： 2013-10-18
上传用户：如果你也听说
BIT_SELFREFRESH EQU (1<<22) ;定义SDRAM自刷新标志位 16 17 ;Pre-defined constants 预定义6种工作模式 18 USERMODE EQU 0x10 ;用户模式 19 FIQMODE EQU 0x11 ;快速中断模式 20 IRQMODE EQU 0x12 ;中断模式 21 SVCMODE EQU 0x13 ;监管模式 22 ABORTMODE EQU 0x17 ;异常中断模式 23 UNDEFMODE EQU 0x1b ;未定义模式 24 25 MODEMASK EQU 0x1f ;模式掩码 26 NOINT EQU 0xc0 ;取消中断 27 28 ;The location of stacks;设置6种工作模式的堆栈的起始地址 29 ;在option.inc中定义了_STACK_BASEADDRESS EQU 0x33ff8000 30 UserStack EQU (_STACK_BASEADDRESS-0x3800) ;0x33ff4800 ~ 31 SVCStack EQU (_STACK_BASEADDRESS-0x2800) ;0x33ff5800 ~ 32 UndefStack EQU (_STACK_BASEADDRESS-0x2400) ;0x33ff5c00 ~ 33 AbortStack EQU (_STACK_BASEADDRESS-0x2000) ;0x33ff6000 ~ 34 IRQStack EQU (_STACK_BASEADDRESS-0x1000) ;0x33ff7000 ~ 35 FIQStack EQU (_STACK_BASEADDRESS-0x0) ;0x33ff8000 ~
上传时间： 2013-10-07
上传用户：m62383408
FeaturesThe following standard features are provided.• Choice of RTOS scheduling policy1. Pre-emptive:Always runs the highest available task. Tasks of identical priorityshare CPU time (fully pre-emptive with round robin time slicing).2. Cooperative:Context switches only occur if a task blocks, or explicitly callstaskYIELD().• Co-routines (light weight tasks that utilise very little RAM).• Message queues• Semaphores [via macros]• Trace visualisation ability (requires more RAM)• Majority of source code common to all supported development tools• Wide range of ports and examples
上传时间： 2013-10-13
上传用户：13162218709
针对使用硬件描述语言进行设计存在的问题，提出一种基于FPGA并采用DSP Builder作为设计工具的数字信号处理器设计方法。并按照Matlab/Simulink/DSP Builder/QuartusⅡ设计流程，设计了一个12阶FIR 低通数字滤波器，通过Quartus 时序仿真及嵌入式逻辑分析仪SignalTapⅡ硬件测试对设计进行了验证。结果表明，所设计的FIR 滤波器功能正确，性能良好。 Abstract: Aiming at the problems in designing DSP using HDL，a method of designing DSP based on FPGA which using DSP Builder as designed tool is pointed out.A 12-order low-pass FIR digital filter was designed according to the process of Matlab/Simulink/DSP Builder/QuartusⅡ, and the design was verified by the timing simulation based on QuartusⅡand practical test based on SignalTapⅡ. The result shows the designed filter is correct in function and good in performance.
上传时间： 2013-11-17
上传用户：lo25643
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
标签： Transceiver Virtex Wizar GTP
上传时间： 2013-10-23
上传用户：leyesome
