PLL锁相环
PLL(Phase Locked Loop)： 为锁相回路或锁相环，用来统一整合时钟信号，使高频器件正常工作，如内存的存取资料等。PLL用于振荡器中的反馈技术。 许多电子设备要正常工作，通常需要外部的...
phase-locked技术资料
📦 资源总数：199
💻 源代码：8761
🔌 电路图：1
📚 phase-locked全部资料 (199个)
ADC模数转换器件Altium Designer AD原理图库元件库
ADC模数转换器件Altium Designer AD原理图库元件库SV text has been written to file : 4.4 - ADC模数转换器件.csvLibrary Comp...
基于滑模观测器与分数阶锁相环的无传感器PMSM矢量控制
Abstract: A sliding mode observer and fractional-order phase-locked loop (FO-PLL) method is proposed...
射频锁相环基础理论
一.基础理论锁相环路（Phase Locked Loop）是一个闭环的相位控制系统，它的输出信号的相位能自动跟踪输入信号相位。系统框图如下：当0，（1）与0：（1）相等时，两矢量以相同的角速度旋转，相...
3 phase motor driver source code with freescale MCU
3 phase motor driver source code with freescale MCU...
phase unwrapping algorithm for SAR interferometry
phase unwrapping algorithm for SAR interferometry...
Control of High Voltage 3-Phase BLDC Motor
Control of High Voltage 3-Phase BLDC Motor...
three-phase Permanent Magnet Synchronous Motor(PMSM) velocity control DSP program
three-phase Permanent Magnet Synchronous Motor(PMSM) velocity control DSP program...
Cycle slip probability of the phase unrapping algorithm
Cycle slip probability of the phase unrapping algorithm...
phase lock loop for coherent detection
phase lock loop for coherent detection...