虫虫首页| 资源下载| 资源专辑| 精品软件
登录| 注册

next

  • Xilinx UltraScale:新一代架构满足您的新一代架构需求(EN)

      中文版详情浏览:http://www.elecfans.com/emb/fpga/20130715324029.html   Xilinx UltraScale:The next-Generation Architecture for Your next-Generation Architecture    The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.   The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.   Some of the UltraScale architecture breakthroughs include:   • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%    • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability   • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization   • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard    • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets   • Greatly enhanced DSP and packet handling   The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.

    标签: UltraScale Xilinx 架构

    上传时间: 2013-11-21

    上传用户:wxqman

  • 基于Quartus II免费IP核的双端口RAM设计实例

      QuartusII中利用免费IP核的设计   作者:雷达室   以设计双端口RAM为例说明。   Step1:打开QuartusII,选择File—New Project Wizard,创建新工程,出现图示对话框,点击next

    标签: Quartus RAM IP核 双端口

    上传时间: 2013-10-18

    上传用户:909000580

  • WP328-FPGA的语音数据融合

      The SDI standards are the predominant standards for uncompressed digital videointerfaces in the broadcast studio and video production center. The first SDI standard,SD-SDI, allowed standard-definition digital video to be transported over the coaxial cableinfrastructure initially installed in studios to carry analog video. next, HD-SDI wasto support high-definition video. Finally, dual link HD-SDI and 3G-SDIdoubled the bandwidth of HD-SDI to support 1080p (50 Hz and 60 Hz) and other videoformats requiring more bandwidth than HD-SDI provides.

    标签: FPGA 328 WP 语音

    上传时间: 2013-12-08

    上传用户:liansi

  • WP312-Xilinx新一代28nm FPGA技术简介

    Xilinx next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.

    标签: Xilinx FPGA 312 WP

    上传时间: 2013-12-07

    上传用户:bruce

  • 先编写MFC DLL

    先编写MFC DLL,打开VC++6.0 => File => New => Project => MFC AppWizzard(dll),在 Project name 里输入Calc =>next => Finish. 好了,现在你打开Workspace的FileView就可以看到已经有Calc.h、Calc.cpp、stdafx.h、stdafx.cpp这4个文件了.

    标签: MFC DLL 编写

    上传时间: 2013-12-21

    上传用户:13681659100

  • 本程序将用户信息设计成一个类

    本程序将用户信息设计成一个类,使用对象模拟对 象数据库,将用户信息保存到数据文件中。并实现打开 文件,保存文本,添加&删除用户信息等功能。 在运行的过程中,用户须先填上自己的姓名、性别 ,然后选择自己所在省份、城市。点击“Add”按钮, 该用户信息即可添加进面板左边的文本区,点击 “Delete”时,可删除该用户的信息,点击“Open”可 打开一个文件,点“Prior”可将该用户信息上移一行, “next”下移一行,“First”上移至文本区第一行, “Last”信息下移至最后一行,“Save”保存左边的文 件为一个文本文档。

    标签: 程序 用户

    上传时间: 2015-03-31

    上传用户:253189838

  • ARM下 Implement matrix multiplication of 2 square matrices, with data read from an input file and pri

    ARM下 Implement matrix multiplication of 2 square matrices, with data read from an input file and printed both to the console and to an output file. • Assume a file with correct data (no garbage, characters, etc.). • you must check and provide appropriate execution for 2 extra cases, namely when the matrix size given is either “0” , or when the size is greater than the maximum handled of “5” . In these 2 cases you must implement the following behaviour: o If size = 0, then print a message “Size = 0 is unacceptable” and continue by reading the next size for the next 2 matrices (if not end of file). o If size >5, then print two messages: “Size is too big - unacceptable”. Then read and discard the next (size2 ) integers and continue by reading the next size for the next 2 matrices (if not end of file).

    标签: multiplication Implement matrices matrix

    上传时间: 2014-08-30

    上传用户:dsgkjgkjg

  • The Audio File Library provides a uniform programming interface to standard digital audio file form

    The Audio File Library provides a uniform programming interface to standard digital audio file formats. This library allows the processing of audio data to and from audio files of many common formats (currently AIFF, AIFF-C, WAVE, next/Sun .snd/.au, IRCAM, AVR, Amiga IFF/8SVX, and NIST SPHERE). The library also supports compression (currently G.711 mu-law and A-law and IMA and MS ADPCM) as well as PCM formats of all flavors (signed and unsigned integer, single- and double-precision floating point).

    标签: programming interface provides standard

    上传时间: 2014-12-06

    上传用户:a6697238

  • This program demonstrates some function approximation capabilities of a Radial Basis Function Networ

    This program demonstrates some function approximation capabilities of a Radial Basis Function Network. The user supplies a set of training points which represent some "sample" points for some arbitrary curve. next, the user specifies the number of equally spaced gaussian centers and the variance for the network. Using the training samples, the weights multiplying each of the gaussian basis functions arecalculated using the pseudo-inverse (yielding the minimum least-squares solution). The resulting network is then used to approximate the function between the given "sample" points.

    标签: approximation demonstrates capabilities Function

    上传时间: 2014-01-01

    上传用户:zjf3110

  • The EM algorithm is short for Expectation-Maximization algorithm. It is based on an iterative optimi

    The EM algorithm is short for Expectation-Maximization algorithm. It is based on an iterative optimization of the centers and widths of the kernels. The aim is to optimize the likelihood that the given data points are generated by a mixture of Gaussians. The numbers next to the Gaussians give the relative importance (amplitude) of each component.

    标签: algorithm Expectation-Maximization iterative optimi

    上传时间: 2015-06-17

    上传用户:独孤求源