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multiple-Input

  • An easy way to work with Exter

    Internal Interrupts are used to respond to asynchronous requests from a certain part of themicrocontroller that needs to be serviced. Each peripheral in the TriCore as well as theBus Control Unit, the Debug Unit, the Peripheral Control Processor (PCP) and the CPUitself can generate an Interrupt Request.So what is an external Interrupt?An external Interrupt is something alike as the internal Interrupt. The difference is that anexternal Interrupt request is caused by an external event. Normally this would be a pulseon Port0 or Port1, but it can be even a signal from the input buffer of the SSC, indicatingthat a service is requested.The User’s Manual does not explain this aspect in detail so this ApNote will explain themost common form of an external Interrupt request. This ApNote will show that there is aneasy way to react on a pulse on Port0 or Port1 and to create with this impulse an InterruptService Request. Later in the second part of the document, you can find hints on how todebounce impulses to enable the use of a simple switch as the input device.Note: You will find additional information on how to setup the Interrupt System in theApNote “First steps through the TriCore Interrupt System” (AP3222xx)1. It would gobeyond the scope of this document to explain this here, but you will find selfexplanatoryexamples later on.

    标签: Exter easy work with

    上传时间: 2013-10-27

    上传用户:zhangyigenius

  • 用外部设备设置32位微控制器TriCore的中断的指令及方法

    The Infineon TriCore provides an Interrupt System with a high safety standard. Thisdocument contains some instructions on how to initiate an Interrupt from an externaldevice. First it will show you how to trigger an Interrupt Service Request by an impulseon Port 0 or Port 1. Then in the second part of the document you can find hints how todebounce impulses to enable the use of a simple switch as input device.Authors: Thomas Bliem, CQ Nguyen / Infineon SMI MD Apps

    标签: TriCore 外部设备 中断 微控制器

    上传时间: 2013-11-05

    上传用户:uuuuuuu

  • 驱动程序与应用程序的接口

    有两种方式可以让设备和应用程序之间联系:1. 通过为设备创建的一个符号链;2. 通过输出到一个接口WDM驱动程序建议使用输出到一个接口而不推荐使用创建符号链的方法。这个接口保证PDO的安全,也保证安全地创建一个惟一的、独立于语言的访问设备的方法。一个应用程序使用Win32APIs来调用设备。在某个Win32 APIs和设备对象的分发函数之间存在一个映射关系。获得对设备对象访问的第一步就是打开一个设备对象的句柄。 用符号链打开一个设备的句柄为了打开一个设备,应用程序需要使用CreateFile。如果该设备有一个符号链出口,应用程序可以用下面这个例子的形式打开句柄:hDevice = CreateFile("\\\\.\\OMNIPORT3",  GENERIC_READ | GENERIC_WRITE,FILE_SHARE_READ,  NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL ,NULL);文件路径名的前缀“\\.\”告诉系统本调用希望打开一个设备。这个设备必须有一个符号链,以便应用程序能够打开它。有关细节查看有关Kdevice和CreateLink的内容。在上述调用中第一个参数中前缀后的部分就是这个符号链的名字。注意:CreatFile中的第一个参数不是Windows 98/2000中驱动程序(.sys文件)的路径。是到设备对象的符号链。如果使用DriverWizard产生驱动程序,它通常使用类KunitizedName来构成设备的符号链。这意味着符号链名有一个附加的数字,通常是0。例如:如果链接名称的主干是L“TestDevice”那么在CreateFile中的串就该是“\\\\.\\TestDevice0”。如果应用程序需要被覆盖的I/O,第六个参数(Flags)必须或上FILE_FLAG_OVERLAPPED。 使用一个输出接口打开句柄用这种方式打开一个句柄会稍微麻烦一些。DriverWorks库提供两个助手类来使获得对该接口的访问容易一些,这两个类是CDeviceInterface, 和 CdeviceInterfaceClass。CdeviceInterfaceClass类封装了一个设备信息集,该信息集包含了特殊类中的所有设备接口信息。应用程序能有用CdeviceInterfaceClass类的一个实例来获得一个或更多的CdeviceInterface类的实例。CdeviceInterface类是一个单一设备接口的抽象。它的成员函数DevicePath()返回一个路径名的指针,该指针可以在CreateFile中使用来打开设备。下面用一个小例子来显示这些类最基本的使用方法:extern GUID TestGuid;HANDLE OpenByInterface(  GUID* pClassGuid,  DWORD instance,  PDWORD pError){  CDeviceInterfaceClass DevClass(pClassGuid, pError);  if (*pError != ERROR_SUCCESS)    return INVALID_HANDLE_VALUE;  CDeviceInterface DevInterface(&DevClass, instance, pError);  if (*pError != ERROR_SUCCESS)    return INVALID_HANDLE_VALUE;  cout << "The device path is "    << DevInterface.DevicePath()    << endl;   HANDLE hDev;  hDev = CreateFile(   DevInterface.DevicePath(),    GENERIC_READ | GENERIC_WRITE,    FILE_SHARE_READ | FILE_SHARE_WRITE,    NULL,    OPEN_EXISTING,    FILE_ATTRIBUTE_NORMAL,    NULL  );  if (hDev == INVALID_HANDLE_VALUE)    *pError = GetLastError();  return hDev;} 在设备中执行I/O操作一旦应用程序获得一个有效的设备句柄,它就能使用Win32 APIs来产生到设备对象的IRPs。下面的表显示了这种对应关系。Win32 API  DRIVER_FUNCTION_xxxIRP_MJ_xxx  KDevice subclass member function CreateFile  CREATE  Create ReadFile  READ  Read WriteFile  WRITE  Write DeviceIoControl  DEVICE_CONTROL  DeviceControl CloseHandle  CLOSECLEANUP  CloseCleanUp 需要解释一下设备类成员的Close和CleanUp:CreateFile使内核为设备创建一个新的文件对象。这使得多个句柄可以映射同一个文件对象。当这个文件对象的最后一个用户级句柄被撤销后,I/O管理器调用CleanUp。当没有任何用户级和核心级的对文件对象的访问的时候,I/O管理器调用Close。如果被打开的设备不支持指定的功能,则调用相应的Win32将引起错误(无效功能)。以前为Windows95编写的VxD的应用程序代码中可能会在打开设备的时候使用FILE_FLAG_DELETE_ON_CLOSE属性。在Windows NT/2000中,建议不要使用这个属性,因为它将导致没有特权的用户企图打开这个设备,这是不可能成功的。I/O管理器将ReadFile和WriteFile的buff参数转换成IRP域的方法依赖于设备对象的属性。当设备设置DO_DIRECT_IO标志,I/O管理器将buff锁住在存储器中,并且创建了一个存储在IRP中的MDL域。一个设备可以通过调用Kirp::Mdl来存取MDL。当设备设置DO_BUFFERED_IO标志,设备对象分别通过KIrp::BufferedReadDest或 KIrp::BufferedWriteSource为读或写操作获得buff地址。当设备不设置DO_BUFFERED_IO标志也不设置DO_DIRECT_IO,内核设置IRP 的UserBuffer域来对应ReadFile或WriteFile中的buff参数。然而,存储区并没有被锁住而且地址只对调用进程有效。驱动程序可以使用KIrp::UserBuffer来存取IRP域。对于DeviceIoControl调用,buffer参数的转换依赖于特殊的I/O控制代码,它不在设备对象的特性中。宏CTL_CODE(在winioctl.h中定义)用来构造控制代码。这个宏的其中一个参数指明缓冲方法是METHOD_BUFFERED, METHOD_IN_DIRECT, METHOD_OUT_DIRECT, 或METHOD_NEITHER。下面的表显示了这些方法和与之对应的能获得输入缓冲与输出缓冲的KIrp中的成员函数:Method  Input Buffer Parameter  Output Buffer Parameter METHOD_BUFFERED  KIrp::IoctlBuffer KIrp::IoctlBuffer METHOD_IN_DIRECT  KIrp::IoctlBuffer KIrp::Mdl METHOD_OUT_DIRECT  KIrp::IoctlBuffer KIrp::Mdl METHOD_NEITHER  KIrp::IoctlType3InputBuffer KIrp::UserBuffer 如果控制代码指明METHOD_BUFFERED,系统分配一个单一的缓冲来作为输入与输出。驱动程序必须在向输出缓冲放数据之前拷贝输入数据。驱动程序通过调用KIrp::IoctlBuffer获得缓冲地址。在完成时,I/O管理器从系统缓冲拷贝数据到提供给Ring 3级调用者使用的缓冲中。驱动程序必须在结束前存储拷贝到IRP的Information成员中的数据个数。如果控制代码不指明METHOD_IN_DIRECT或METHOD_OUT_DIRECT,则DeviceIoControl的参数呈现不同的含义。参数InputBuffer被拷贝到一个系统缓冲,这个缓冲驱动程序可以通过调用KIrp::IoctlBuffer。参数OutputBuffer被映射到KMemory对象,驱动程序对这个对象的访问通过调用KIrp::Mdl来实现。对于METHOD_OUT_DIRECT,调用者必须有对缓冲的写访问权限。注意,对METHOD_NEITHER,内核只提供虚拟地址;它不会做映射来配置缓冲。虚拟地址只对调用进程有效。这里是一个用METHOD_BUFFERED的例子:首先,使用宏CTL_CODE来定义一个IOCTL代码:#define IOCTL_MYDEV_GET_FIRMWARE_REV \CTL_CODE (FILE_DEVICE_UNKNOWN,0,METHOD_BUFFERED,FILE_ANY_ACCESS)现在使用一个DeviceIoControl调用:BOOLEAN b;CHAR FirmwareRev[60];ULONG FirmwareRevSize;b = DeviceIoControl(hDevice, IOCTL_MYDEV_GET_VERSION_STRING,  NULL, // no input  注意,这里放的是包含有执行操作命令的字符串指针  0, FirmwareRev,      //这里是output串指针,存放从驱动程序中返回的字符串。sizeof(FirmwareRev),& FirmwareRevSize,  NULL // not overlapped I/O );如果输出缓冲足够大,设备拷贝串到里面并将拷贝的资结束设置到FirmwareRevSize中。在驱动程序中,代码看起来如下所示:const char* FIRMWARE_REV = "FW 16.33 v5";NTSTATUS MyDevice::DeviceControl( KIrp I ){  ULONG fwLength=0;  switch ( I.IoctlCode() )  {    case IOCTL_MYDEV_GET_FIRMWARE_REV:      fwLength = strlen(FIRMWARE_REV)+1;      if (I.IoctlOutputBufferSize() >= fwLength)      {        strcpy((PCHAR)I.IoctlBuffer(),FIRMWARE_REV);        I.Information() = fwLength;         return I.Complete(STATUS_SUCCESS);      }      else      {              }    case . . .   } }

    标签: 驱动程序 应用程序 接口

    上传时间: 2013-10-17

    上传用户:gai928943

  • 3.3v看门狗芯片

    The STWD100 watchdog timer circuits are self-contained devices which prevent systemfailures that are caused by certain types of hardware errors (non-responding peripherals,bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.).The STWD100 watchdog timer has an input, WDI, and an output, WDO (see Figure 2). Theinput is used to clear the internal watchdog timer periodically within the specified timeoutperiod, twd (see Section 3: Watchdog timing). While the system is operating correctly, itperiodically toggles the watchdog input, WDI. If the system fails, the watchdog timer is notreset, a system alert is generated and the watchdog output, WDO, is asserted (seeSection 3: Watchdog timing).The STWD100 circuit also has an enable pin, EN (see Figure 2), which can enable ordisable the watchdog functionality. The EN pin is connected to the internal pull-downresistor. The device is enabled if the EN pin is left floating.

    标签: 3.3 看门狗 芯片

    上传时间: 2013-10-22

    上传用户:taiyang250072

  • 基于DSP与FPGA的多视频通道的切换控制

    为了扩大监控范围,提高资源利用率,降低系统成本,提出了一种多通道视频切换的解决方案。首先从视频信号分离出行场信号,然后根据行场信号由DSP和FPGA产生控制信号,控制多路视频通道之间的切换,从而实现让一个视频处理器同时监控不同场景。实验结果表明,该方案可以在视频监控告警系统中稳定、可靠地实现视频通道的切换。 Abstract:  To expand the scope of monitoring, improve resource utilization, reduce system cost, a multiple video channels signal switching method is pointed out in this paper. First, horizontal sync signal and field sync signal from the video signal are separated, then control signal according to the sync signal by DSP and FPGA is generated to control the switching between multiple video channels. Thus, it achieves to make a video processor to monitor different place. Experimental results show that the method can realize video channel switching reliably, and is applied in the video monitoring warning system successfully.

    标签: FPGA DSP 视频通道 切换控制

    上传时间: 2013-11-09

    上传用户:不懂夜的黑

  • XAPP740利用AXI互联设计高性能视频系统

    This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX  and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board

    标签: XAPP 740 AXI 互联

    上传时间: 2013-11-14

    上传用户:fdmpy

  • 基于CPLD的QDPSK调制解调电路设计

    为了在CDMA系统中更好地应用QDPSK数字调制方式,在分析四相相对移相(QDPSK)信号调制解调原理的基础上,设计了一种QDPSK调制解调电路,它包括串并转换、差分编码、四相载波产生和选相、相干解调、差分译码和并串转换电路。在MAX+PLUSⅡ软件平台上,进行了编译和波形仿真。综合后下载到复杂可编程逻辑器件EPM7128SLC84-15中,测试结果表明,调制电路能正确选相,解调电路输出数据与QDPSK调制输入数据完全一致,达到了预期的设计要求。 Abstract:  In order to realize the better application of digital modulation mode QDPSK in the CDMA system, a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase,and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.

    标签: QDPSK CPLD 调制解调 电路设计

    上传时间: 2014-01-13

    上传用户:qoovoop

  • 8259 VHDL代码

    a8259 可编程中断控制 altera提供 The a8259 is designed to simplify the implementation of the interrupt interface  in 8088 and 8086  based microcomputer systems. The device is known as a programmable interrupt controller.  The a8259 receives and prioritizes up to 8 interrupts,  and in the cascade mode, this can be expanded up to  64 interrupts. An asynchronous reset and a clock input have been added to improve operation and reliability.

    标签: 8259 VHDL 代码

    上传时间: 2014-11-29

    上传用户:zhyiroy

  • tcp ip协议详解 中文版PDF

    很多不同的厂家生产各种型号的计算机,它们运行完全不同的操作系统,但TCP.IP协议族允许它们互相进行通信。这一点很让人感到吃惊,因为它的作用已远远超出了起初的设想。T C P / I P起源于6 0年代末美国政府资助的一个分组交换网络研究项目,到9 0年代已发展成为计算机之间最常应用的组网形式。它是一个真正的开放系统,因为协议族的定义及其多种实现可以不用花钱或花很少的钱就可以公开地得到。它成为被称作“全球互联网”或“因特网(Internet)”的基础,该广域网(WA N)已包含超过1 0 0万台遍布世界各地的计算机。本章主要对T C P / I P协议族进行概述,其目的是为本书其余章节提供充分的背景知识。 TCP.IP协议 缩略语 ACK (ACKnowledgment) TCP首部中的确认标志 API (Application Programming Interface) 应用编程接口 ARP (Address Resolution Protocol) 地址解析协议 ARPANET(Defense Advanced Research Project Agency NETwork) (美国)国防部远景研究规划局 AS (Autonomous System) 自治系统 ASCII (American Standard Code for Information Interchange) 美国信息交换标准码 ASN.1 (Abstract Syntax Notation One) 抽象语法记法1 BER (Basic Encoding Rule) 基本编码规则 BGP (Border Gateway Protocol) 边界网关协议 BIND (Berkeley Internet Name Domain) 伯克利I n t e r n e t域名 BOOTP (BOOTstrap Protocol) 引导程序协议 BPF (BSD Packet Filter) BSD 分组过滤器 CIDR (Classless InterDomain Routing) 无类型域间选路 CIX (Commercial Internet Exchange) 商业互联网交换 CLNP (ConnectionLess Network Protocol) 无连接网络协议 CRC (Cyclic Redundancy Check) 循环冗余检验 CSLIP (Compressed SLIP) 压缩的S L I P CSMA (Carrier Sense Multiple Access) 载波侦听多路存取 DCE (Data Circuit-terminating Equipment) 数据电路端接设备 DDN (Defense Data Network) 国防数据网 DF (Don’t Fragment) IP首部中的不分片标志 DHCP (Dynamic Host Configuration Protocol) 动态主机配置协议 DLPI (Data Link Provider Interface) 数据链路提供者接口 DNS (Domain Name System) 域名系统 DSAP (Destination Service Access Point) 目的服务访问点 DSLAM (DSL Access Multiplexer) 数字用户线接入复用器 DSSS (Direct Sequence Spread Spectrum) 直接序列扩频 DTS (Distributed Time Service) 分布式时间服务 DVMRP (Distance Vector Multicast Routing Protocol) 距离向量多播选路协议 EBONE (European IP BackbONE) 欧洲I P主干网 EOL (End of Option List) 选项清单结束 EGP (External Gateway Protocol) 外部网关协议 EIA (Electronic Industries Association) 美国电子工业协会 FCS (Frame Check Sequence) 帧检验序列 FDDI (Fiber Distributed Data Interface) 光纤分布式数据接口 FIFO (First In, First Out) 先进先出 FIN (FINish) TCP首部中的结束标志 FQDN (Full Qualified Domain Name) 完全合格的域名 FTP (File Transfer Protocol) 文件传送协议 HDLC (High-level Data Link Control) 高级数据链路控制 HELLO 选路协议 IAB (Internet Architecture Board) Internet体系结构委员会 IANA (Internet Assigned Numbers Authority) Internet号分配机构 ICMP (Internet Control Message Protocol) Internet控制报文协议 IDRP (InterDomain Routing Protocol) 域间选路协议 IEEE (Institute of Electrical and Electronics Engineering) (美国)电气与电子工程师协会 IEN (Internet Experiment Notes) 互联网试验注释 IESG (Internet Engineering Steering Group) Internet工程指导小组 IETF (Internet Engineering Task Force) Internet工程专门小组 IGMP (Internet Group Management Protocol) Internet组管理协议 IGP (Interior Gateway Protocol) 内部网关协议 IMAP (Internet Message Access Protocol) Internet报文存取协议 IP (Internet Protocol) 网际协议 I RTF (Internet Research Task Force) Internet研究专门小组 IS-IS (Intermediate System to Intermediate System Protocol) 中间系统到中间系统协议 ISN (Initial Sequence Number) 初始序号 ISO (International Organization for Standardization) 国际标准化组织 ISOC (Internet SOCiety) Internet协会 LAN (Local Area Network) 局域网 LBX (Low Bandwidth X) 低带宽X LCP (Link Control Protocol) 链路控制协议 LFN (Long Fat Net) 长肥网络 LIFO (Last In, First Out) 后进先出 LLC (Logical Link Control) 逻辑链路控制 LSRR (Loose Source and Record Route) 宽松的源站及记录路由 MBONE (Multicast Backbone On the InterNEt) Internet上的多播主干网 MIB (Management Information Base) 管理信息库 MILNET (MILitary NETwork) 军用网 MIME (Multipurpose Internet Mail Extensions) 通用I n t e r n e t邮件扩充 MSL (Maximum Segment Lifetime) 报文段最大生存时间 MSS (Maximum Segment Size) 最大报文段长度 M TA (Message Transfer Agent) 报文传送代理 MTU (Maximum Transmission Unit) 最大传输单元 NCP (Network Control Protocol) 网络控制协议 NFS (Network File System) 网络文件系统 NIC (Network Information Center) 网络信息中心 NIT (Network Interface Tap) 网络接口栓(S u n公司的一个程序) NNTP (Network News Transfer Protocol) 网络新闻传送协议 NOAO (National Optical Astronomy Observatories) 国家光学天文台 NOP (No Operation) 无操作 NSFNET (National Science Foundation NETwork) 国家科学基金网络 NSI (NASA Science Internet) (美国)国家宇航局I n t e r n e t NTP (Network Time Protocol) 网络时间协议 NVT (Network Virtual Terminal) 网络虚拟终端 OSF (Open Software Foudation) 开放软件基金 OSI (Open Systems Interconnection) 开放系统互连 OSPF (Open Shortest Path First) 开放最短通路优先 PAWS (Protection Against Wrapped Sequence number) 防止回绕的序号 PDU (Protocol Data Unit) 协议数据单元 POSIX (Portable Operating System Interface) 可移植操作系统接口 PPP (Point-to-Point Protocol) 点对点协议 PSH (PuSH) TCP首部中的急迫标志 RARP (Reverse Address Resolution Protocol) 逆地址解析协议 RFC (Request For Comments) Internet的文档,其中的少部分成为标准文档 RIP (Routing Information Protocol) 路由信息协议 RPC (Remote Procedure Call) 远程过程调用 RR (Resource Record) 资源记录 RST (ReSeT) TCP首部中的复位标志 RTO (Retransmission Time Out) 重传超时 RTT (Round-Trip Time) 往返时间 SACK (Selective ACKnowledgment) 有选择的确认 SLIP (Serial Line Internet Protocol) 串行线路I n t e r n e t协议 SMI (Structure of Management Information) 管理信息结构 SMTP (Simple Mail Transfer Protocol) 简单邮件传送协议 SNMP (Simple Network Management Protocol) 简单网络管理协议 SSAP (Source Service Access Point) 源服务访问点 SSRR (Strict Source and Record Route) 严格的源站及记录路由 SWS (Silly Window Syndrome) 糊涂窗口综合症 SYN (SYNchronous) TCP首部中的同步序号标志 TCP (Transmission Control Protocol) 传输控制协议 TFTP (Trivial File Transfer Protocol) 简单文件传送协议 TLI (Transport Layer Interface) 运输层接口 TTL (Ti m e - To-Live) 生存时间或寿命 TUBA (TCP and UDP with Bigger Addresses) 具有更长地址的T C P和U D P Telnet 远程终端协议 UA (User Agent) 用户代理 UDP (User Datagram Protocol) 用户数据报协议 URG (URGent) TCP首部中的紧急指针标志 UTC (Coordinated Universal Time) 协调的统一时间 UUCP (Unix-to-Unix CoPy) Unix到U n i x的复制 WAN (Wide Area Network) 广域网 WWW (World Wide Web) 万维网 XDR (eXternal Data Representation) 外部数据表示 XID (transaction ID) 事务标识符 XTI (X/Open Transport Layer Interface) X/ O p e n运输层接口

    标签: tcp 协议

    上传时间: 2013-11-13

    上传用户:tdyoung

  • XAPP807-封装最小的三态以太网MAC处理引擎

    The Tri-Mode Ethernet MAC (TEMAC) UltraController-II module is a minimal footprint,embedded network processing engine based on the PowerPC™ 405 (PPC405) processor coreand the TEMAC core embedded within a Virtex™-4 FX Platform FPGA. The TEMACUltraController-II module connects to an external PHY through Gigabit Media IndependentInterface (GMII) and Management Data Input/Output (MDIO) interfaces and supports tri-mode(10/100/1000 Mb/s) Ethernet. Software running from the processor cache reads and writesthrough an On-Chip Memory (OCM) interface to two FIFOs that act as buffers between thedifferent clock domains of the PPC405 OCM and the TEMAC.

    标签: XAPP 807 MAC 封装

    上传时间: 2013-10-26

    上传用户:yuzsu