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  • Xilinx UltraScale:新一代架构满足您的新一代架构需求(EN)

      中文版详情浏览:http://www.elecfans.com/emb/fpga/20130715324029.html   Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture    The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.   The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.   Some of the UltraScale architecture breakthroughs include:   • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%    • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability   • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization   • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard    • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets   • Greatly enhanced DSP and packet handling   The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.

    标签: UltraScale Xilinx 架构

    上传时间: 2013-11-13

    上传用户:瓦力瓦力hong

  • 基于FPGA+DSP模式的智能相机设计

    针对嵌入式机器视觉系统向独立化、智能化发展的要求,介绍了一种嵌入式视觉系统--智能相机。基于对智能相机体系结构、组成模块和图像采集、传输和处理技术的分析,对国内外的几款智能相机进行比较。综合技术发展现状,提出基于FPGA+DSP模式的硬件平台,并提出智能相机的发展方向。分析结果表明,该系统设计可以实现脱离PC运行,完成图像获取与分析,并作出相应输出。 Abstract:  This paper introduced an embedded vision system-intelligent camera ,which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera architecture, component modules and image acquisition, transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad, the paper proposed the hardware platform based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design, the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding output.

    标签: FPGA DSP 模式 智能相机

    上传时间: 2013-10-24

    上传用户:bvdragon

  • 基于以太网的虚拟示波器设计

    为提升虚拟仪器传输速率与实时性能,扩展监测范围,在VC的软件平台上设计了一种全功能虚拟示波器。与传统虚拟示波器相比,该系统采用嵌入式系统完成信号采集,采用工业以太网为传输介质,通过线性插值算法和多线程编程思想,实现波形显示、参数计算、频谱分析以及波形存储及回放功能。实验结果表明,该虚拟示波器可以实现20 kHz采样频率下的波形精确显示,达到预期的各项指标。 Abstract:  o enhance the transfer rate and real-time of virtual instrument performance, expand scope of monitoring, this paper uses the VCs software platform to design a fully functional virtual oscilloscope. Compared with traditional virtual oscilloscope, this system adopts the embedded system to complete the data acquisition, industrial Ethernet as the transmission medium used by the linear interpolation algorithm and multi-threaded programming ideas, namely to achieve waveform display, parameter calculation, spectrum analysis and waveform storage and playback. Experimental results show that the virtual oscilloscope can accurately display the waveform with 20kHz sampling frequency, and achieve the desired targets.

    标签: 以太网 虚拟 波器设计

    上传时间: 2013-11-25

    上传用户:wbwyl

  • TMS-S231-512G

    致力于提供高速信号处理解决方案的北京拓目科技有限公司(Beijing Topmoo Tech Co. Ltd)在2011年推出基于FLASH阵列存储的高端固态存储产品TMS-F231-160G之后,近日宣布推出其入门级固态存储产品TMS-S231-512G。 在容量选择上,TMS-F231-160G可以通过更换PIN2PIN的FLASH芯片而达到扩容目的,但是SLC FLASH成本高居不下,在目前高速发展的工业相机领域,难以推广普及。为了推动高速工业相机存储市场的发展,拓目科技发布了基于SATA接口的SSD盘存储系统TMS-S231-512G,随着消费电子的发展,SSD的单盘容量不断的扩大,价格不断的降低,必然能使TMS-S231-512G得到广泛的应用。 “TMS-S231-512G是一款专门针对航空拍摄、工业照相、汽车碰撞实验等需要高速图像采集、存储的场合而开发的固态存储设备”拓目科技产品经理Lemon Chan介绍道,“该产品的单盘存储容量最高可达512GB,单盘存储带宽则最高可达250MB/s,在该带宽支持条件下,TMS-S231-512G最高能支持1280x1024@200fps的连续拍照模式,几乎适用于所有需要高速图像采集的场合”。 “目前,Camera Link接口在航空相机、工业相机等领域得到广泛应用。与此同时,TMS-S231-512G板载两个SFP光纤接口,最高可支持5Gbps的有效数据吞吐率。”拓目科技研发总监Steven Wu介绍道,“除了硬件板卡以外,拓目科技还提供一整套完整的客户端解决方案,以方便客户能够轻易地对设备进行管控,同时方便客户对记录下来的数据进行预览、下载等操作”。 “与国外同类产品相比,TMS-S231-512G除了大容量、高带宽等优点以外,另一大优势在于其极强的可定制性。TMS-S231-512G从硬件设计到软件开发,所有的核心技术都由拓目科技研发团队自主开发,相比于国外同类产品,拓目科技无论在产品的可定制性还是售后技术支持方面,都具有较大的优势”Steven Wu补充道。 同时,该款产品所有器件均采用工业级宽温芯片,温度、振动等环境适应性试验均已顺利通过,能最大程度地保证产品在恶劣环境下的可靠性。 TMS-S231系列产品特点 1, 采用业界领先的掉电保护技术,令您的数据安全无忧 2, 性能卓越,拥有单盘高达250MB/s的写带宽 3, 单盘64GB~512GB大容量可选,存储容量大小也可以根据用户需求定制 4, 支持Camera Link视频输入接口 5, 支持DVI显示接口 6, 支持SFP光纤接口 7, 支持2个SSD盘 8, 支持1个千兆以太网口 9, 满足各种恶劣环境应用要求,能在高温度、多灰尘、高海拔、强振动等应用场合下正常使用 TMS-S231采用12V电源适配器供电,功耗小于10W,TMS-S231集成度非常高,产品体积仅为260mm x 180mm x 45mm,如上图所示。TMS-S231现已进入大批量生产阶段并随时接受客户试用申请与订货。

    标签: TMS-S 231 512

    上传时间: 2013-11-12

    上传用户:a155166

  • 快速跳频通信系统同步技术研究

    同步技术是跳频通信系统的关键技术之一,尤其是在快速跳频通信系统中,常规跳频通信通过同步字头携带相关码的方法来实现同步,但对于快跳频来说,由于是一跳或者多跳传输一个调制符号,难以携带相关码。对此引入双跳频图案方法,提出了一种适用于快速跳频通信系统的同步方案。采用短码携带同步信息,克服了快速跳频难以携带相关码的困难。分析了同步性能,仿真结果表明该方案同步时间短、虚警概率低、捕获概率高,同步性能可靠。 Abstract:  Synchronization is one of the key techniques to frequency-hopping communication system, especially in the fast frequency hopping communication system. In conventional frequency hopping communication systems, synchronization can be achieved by synchronization-head which can be used to carry the synchronization information, but for the fast frequency hopping, Because modulation symbol is transmitted by per hop or multi-hop, it is difficult to carry the correlation code. For the limitation of fast frequency hopping in carrying correlation code, a fast frequency-hopping synchronization scheme with two hopping patterns is proposed. The synchronization information is carried by short code, which overcomes the difficulty of correlation code transmission in fast frequency-hopping. The performance of the scheme is analyzed, and simulation results show that the scheme has the advantages of shorter synchronization time, lower probability of false alarm, higher probability of capture and more reliable of synchronization.

    标签: 快速跳频 同步技术 通信系统

    上传时间: 2013-11-23

    上传用户:mpquest

  • LTC3207,LTC3207-1用户指南

      The LTC®3207/LTC3207-1 is a 600mA LED/Camera driverwhich illuminates 12 Universal LEDs (ULEDs) and onecamera fl ash LED. The ULEDs are considered universalbecause they may be individually turned on or off, setin general purpose output (GPO) mode, set to blink at aselected on-time and period, or gradate on and off at aselected gradation rate. This device also has an externalenable (ENU) pin that may be used to blink, gradate, orturn on/off the LEDs without using the I2C bus. This may beuseful if the microprocessor is in sleep or standby mode. Ifused properly, these features may save valuable memoryspace, programming time, and reduce the I2C traffi c.

    标签: 3207 LTC 用户

    上传时间: 2014-01-04

    上传用户:LANCE

  • LPC315x系列ARM微控制器用户手册

    The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.

    标签: 315x LPC 315 ARM

    上传时间: 2014-01-17

    上传用户:Altman

  • 时钟恢复设计_英文版

    Today in many applications such as network switches, routers, multi-computers,and processor-memory interfaces, the ability to integrate hundreds of multi-gigabit I/Os is desired to make better use of the rapidly advancing IC technology.

    标签: 时钟恢复 英文

    上传时间: 2013-10-30

    上传用户:ysjing

  • H-JTAG调试软件下载

    ARM通讯   H-JTAG 是一款简单易用的的调试代理软件,功能和流行的MULTI-ICE 类似。H-JTAG 包括两个工具软件:H-JTAG SERVER 和H-FLASHER。其中,H-JTAG SERVER 实现调试代理的功能,而H-FLASHER则实现了FLASH 烧写的功能。H-JTAG 的基本结构如下图1-1所示。  H-JTAG支持所有基于ARM7 和ARM9的芯片的调试,并且支持大多数主流的ARM调试软件,如ADS、RVDS、IAR 和KEIL。通过灵活的接口配置,H-JTAG 可以支持WIGGLER,SDT-JTAG 和用户自定义的各种JTAG 调试小板。同时,附带的H-FLASHER 烧写软件还支持常用片内片外FLASH 的烧写。使用H-JTAG,用户能够方便的搭建一个简单易用的ARM 调试开发平台。H-JTAG 的功能和特定总结如下: 1. 支持 RDI 1.5.0 以及 1.5.1; 2. 支持所有ARM7 以及 ARM9 芯片; 3. 支持 THUMB 以及ARM 指令; 4. 支持 LITTLE-ENDIAN 以及 BIG-ENDIAN; 5. 支持 SEMIHOSTING; 6. 支持 WIGGLER, SDT-JTAG和用户自定义JTAG调试板; 7. 支持 WINDOWS 9.X/NT/2000/XP; 8.支持常用FLASH 芯片的编程烧写; 9. 支持LPC2000 和AT91SAM 片内FLASH 的自动下载;

    标签: H-JTAG 调试软件

    上传时间: 2014-12-01

    上传用户:Miyuki

  • Xilinx UltraScale:新一代架构满足您的新一代架构需求(EN)

      中文版详情浏览:http://www.elecfans.com/emb/fpga/20130715324029.html   Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture    The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.   The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.   Some of the UltraScale architecture breakthroughs include:   • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%    • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability   • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization   • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard    • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets   • Greatly enhanced DSP and packet handling   The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.

    标签: UltraScale Xilinx 架构

    上传时间: 2013-11-21

    上传用户:wxqman