3.3v看门狗芯片
The STWD100 watchdog timer circuits are self-contained devices which prevent systemfailures that are caused by certain types of hardware errors (non-r...
The STWD100 watchdog timer circuits are self-contained devices which prevent systemfailures that are caused by certain types of hardware errors (non-r...
针对使用硬件描述语言进行设计存在的问题,提出一种基于FPGA并采用DSP Builder作为设计工具的数字信号处理器设计方法。并按照Matlab/Simulink/DSP Builder/QuartusⅡ设计流程,设计了一个12阶FIR 低通数字滤波器,通过Quartus 时序仿真及嵌入式逻辑分析仪...
中文版详情浏览:http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Archi...
Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express...
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Int...