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This Verilog HDL description implements a UART Version 1.1 : Original Creation 2.1 : added comments
Auditory Simulation Development Computing System version 1.5.2, is based upon a unified re-interpretation in ANSI C o...
Auditory Simulation Development Computing System(unix) version 1.5.2, is based upon a unified re-interpretation in AN...
The final version of UPX scrambler and PE sources in Delphi and flat assembler.
SD Specifications Part E1 SDIO Simplified Specification Version 1.10 April 3, 2006 Technical Commi
RTX51 TINY Version 2 has been completly restructured to gain flexiblity, accelarate performance, and reduce code/data s...
WordWeb thesaurus/dictionary component for Delphi and C++ Builder Version 1.62, freeware The component uses the free...
Good route planning algorithm package. Contained A* and Djistra route finding and improved version.
h264 chinese version,it s useful for the people whose english is not good.