This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
上传时间： 2013-11-01
上传用户：wojiaohs
This application note describes the implementation of a two-dimensional Rank Order filter. Thereference design includes the RTL VHDL implementation of an efficient sorting algorithm. Thedesign is parameterizable for input/output precision, color standards, filter kernel size,maximum horizontal resolution, and implementation options. The rank to be selected can bemodified dynamically, and the actual horizontal resolution is picked up automatically from theinput synchronization signals. The design has a fully synchronous interface through the ce, clk,and rst ports.
上传时间： 2013-12-13
上传用户：逗逗666
本文讨论了如何设计有效的testbench，适合刚接触testbench不久的用户阅读提高 （xilinx公司编写）
标签： Testbenches efficient Writing
上传时间： 2013-10-10
上传用户：123454
The power of programmability gives industrial automation designers a highly efficient， cost-effective alternative to traditional motor control units （MCUs）。 The parallel-processing power， fast computational speeds， and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control algorithms such as Field Oriented Control （FOC）。 Additionally， Xilinx devices lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing （DSP） that can tackle compute-intensive functions such as PID Controller， Clark/Park transforms， and Space Vector PWM. The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving， proven， motor-control reference designs. The kit also shortens the process of developing custom control capabilities， with integrated peripheral functions （Ethernet， PowerLink， and PCI® Express）， a motor-control FPGA mezzanine card （FMC） with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators， and prototyping support for evaluating alternative front-end circuitry.
上传时间： 2013-10-28
上传用户：wujijunshi
为了提高直接转矩控制（DTC）系统定子磁链估计精度，降低电流、电压测量的随机误差，提出了一种基于扩展卡尔曼滤波（EKF）实现异步电机转子位置和速度估计的方法。扩展卡尔曼滤波器是建立在基于旋转坐标系下由定子电流、电压、转子转速和其它电机参量所构成的电机模型上，将定子电流、定子磁链、转速和转子角位置作为状态变量，定子电压为输入变量，定子电流为输出变量，通过对磁链和转速的闭环控制提高定子磁链的估计精度，实现了异步电机的无速度传感器直接转矩控制策略，仿真结果验证了该方法的可行性,提高了直接转矩的控制性能。 Abstract: In order to improve the Direct Torque Control（DTC） system of stator flux estimation accuracy and reduce the current， voltage measurement of random error， a novel method to estimate the speed and rotor position of asynchronous motor based on extended Kalman filter was introduced. EKF was based on d-p axis motor and other motor parameters （state vector: stator current， stator flux linkage， rotor angular speed and position； input: stator voltage； output: staror current). EKF was designed for stator flux and rotor speed estimation in close-loop control. It can improve the estimated accuracy of stator flux. It is possible to estimate the speed and rotor position and implement asynchronous motor drives without position and speed sensors. The simulation results show it is efficient and improves the control performance.
上传时间： 2015-01-02
上传用户：qingdou
sheerdns is a master DNS server whose zone records are stored on a One-Record-Per-File bases. Because of this, it is the simplest of any DNS to configure, the easiest to update, and the most efficient for networks that experience a lot of updates (for example master servers for dynamic IP address ranges). You never have to restart it; any updates are available immediately without having to notify the sheerdns process. 来源: http://freshmeat.net/projects/sheerdns/?topic_id=149 sheerdns是一个主DNS服务器，它的域记录保存在一个One-Record-Per-File（每文件一个记录）的库中。因此，它是最简单的DNS配制，最容易更新，对于有大量更新的网络（如动态IP地址范围的主服务器）来说它是最高效的。你不必重新启动它，任何更新不用通知对应DNS进程就可以立即生效。
标签： One-Record-Per-File sheerdns records Becaus
上传时间： 2015-01-10
上传用户：wyc199288
The ICA/BSS algorithms are pure mathematical formulas, powerful, but rather mechanical procedures: There is not very much left for the user to do after the machinery has been optimally implemented. The successful and efficient use of the ICALAB strongly depends on a priori knowledge, common sense and appropriate use of the preprocessing and postprocessing tools. In other words, it is preprocessing of data and postprocessing of models where expertise is truly ne
标签： mathematical algorithms mechanical procedures
上传时间： 2015-03-30
上传用户：silenthink
Although there has been a lot of AVL tree libraries available now, nearly all of them are meant to work in the random access memory(RAM). Some of them do provide some mechanism for dumping the whole tree into a file and loading it back to the memory in order to make data in that tree persistent. It serves well when there s just small amount of data. When the tree is somewhat bigger, the dumping/loading process could take a lengthy time and makes your mission-critical program less efficient. How about an AVL tree that can directly use the disk for data storage ? If there s something like that, we won t need to read through the whole tree in order to pick up just a little bit imformation(a node), but read only the sectors that are neccssary for locating a certain node and the sectors in which that node lies. This is my initial motivation for writing a storage-media independent AVL Tree. However, as you step forth, you would find that it not only works fine with disks but also fine with memorys, too.
标签： available libraries Although nearly
上传时间： 2014-01-22
上传用户：zhoujunzhen
The HD66773, controller driver LSI, displays 132RGB-by-176 dot graphics on TFT displays in 260,000 colors. The HD66773’s bit-operation functions, 18-bit high-speed bus interface, and high-speed RAMwrite functions enable efficient data transfer and high-speed rewriting of data to the graphic RAM.
标签： displays controller graphics RGB-by
上传时间： 2014-06-19
上传用户：stvnash
一篇05年9月IEEE上发表的论文，题目是Definition of efficient PAPR in OFDM.pdf
上传时间： 2014-01-25
上传用户：zhyiroy
