crc hdl

利用verlilog hdl语言编程

利用verlilog hdl语言编程，完成了8051内核，非常值得学习硬件描述语言的人看看！

标签： verlilog hdl 语言编程

上传时间： 2015-12-10

上传用户：erkuizhang
该代码中有不少关于学习verilog HDL的例子,对初学者有帮助

该代码中有不少关于学习verilog HDL的例子,对初学者有帮助

标签： verilog HDL 代码初学者

上传时间： 2013-12-19

上传用户：asdkin
Verilog HDL课件

Verilog HDL课件，有常见问题说明

标签： Verilog HDL

上传时间： 2013-12-21

上传用户：sdq_123
Verilog HDL的标准

Verilog HDL的标准，比较详细的语法说明

标签： Verilog HDL 标准

上传时间： 2015-12-15

上传用户：xsnjzljj
As the Hardware Description Language (HDL) enhancement activities have increased over the past year,

As the Hardware Description Language (HDL) enhancement activities have increased over the past year, so too has the complexity in determining which language(s) are the best tools for designers and organizations to continue using or to adopt. Many designers and organizations are contemplating whether they should switch from one HDL to another.

标签： Description enhancement activities the

上传时间： 2015-12-15

上传用户：sunjet
Testbenches have become an integral part of the design process, enabling you to verify that your HDL

Testbenches have become an integral part of the design process, enabling you to verify that your HDL model is sufficiently tested before implementing your design and helping you automate the design verification process. It is essential, therefore, that you have confidence your testbench is thoroughly exercising your design. Collecting code coverage statistics during simulation helps to ensure the quality and thoroughness of your tests.

标签： Testbenches enabling integral process

上传时间： 2014-01-25

上传用户：ynzfm
As the Hardware Description Language (HDL) enhancement activities have increased over the past year,

As the Hardware Description Language (HDL) enhancement activities have increased over the past year, so too has the complexity in determining which language(s) are the best tools for designers and organizations to continue using or to adopt. Many designers and organizations are contemplating whether they should switch from one HDL to another.

标签： Description enhancement activities the

上传时间： 2015-12-15

上传用户：SimonQQ
台湾verilog hdl硬件描述性语言

台湾verilog hdl硬件描述性语言，适合有基础的人

标签： verilog hdl 硬件语言

上传时间： 2014-01-09

上传用户：13681659100
采用Verilog HDL硬件语言设计,实现基本的公用电话计费功能,设计完整.

采用Verilog HDL硬件语言设计,实现基本的公用电话计费功能,设计完整.

标签： Verilog HDL 硬件语言设计电话

上传时间： 2014-01-11

上传用户：tzl1975
】　本文主要讨论了Modbus 通信协议的R TU 帧格式中常用的错误校验方法,即循环冗余校验法( CRC) 。提出了Modbus 协议反转CRC 校验的方法,推导了反转CRC 校验快速计算表格,

】　本文主要讨论了Modbus 通信协议的R TU 帧格式中常用的错误校验方法,即循环冗余校验法( CRC) 。提出了Modbus 协议反转CRC 校验的方法,推导了反转CRC 校验快速计算表格,并用C 语言实现了基于快速查表算法的循环冗余校验程序。

标签： Modbus CRC TU 通信协议

上传时间： 2015-12-16

上传用户：498732662