源码文件
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity division is port( div_in:in std_logic; …
cpld 源代码
CPLD采用CMOSEPROM、EEPROM、快闪存储器和SRAM等编程技术，从而构成了高密度、高速度和低功耗的可编程逻辑器件。cPCI总线
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源码文件
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY TOP IS --顶层设计 PORT ( CLK12MHZ : IN …
源码文件
/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that …
源码文件
TFF_1_inst : TFF_1 PORT MAP( clock => clock_sig, aclr => aclr_sig, aset => aset_sig, q => q_sig );
源码文件
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity txmittest is port( tx:out std_logic; …
源码文件
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity divider is port(div_in:in std_logic; d…
源码文件
-- megafunction wizard: %LPM_ROM% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_rom -- =========================…
源码文件
-- megafunction wizard: %LPM_FF% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_ff -- ===========================…
源码文件
-- megafunction wizard: %LPM_CONSTANT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_constant -- ===============…
源码文件
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY Tone IS PORT ( Index : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CODE…