源码文件
/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that …
cpld 源代码
CPLD采用CMOSEPROM、EEPROM、快闪存储器和SRAM等编程技术，从而构成了高密度、高速度和低功耗的可编程逻辑器件。cPCI总线
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源码文件
-- megafunction wizard: %LPM_CONSTANT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_constant -- ===============…
源码文件
---------------------------------------------------------------- -- -- Copyright (c) 1992,1993,1994, Exemplar Logic Inc. All rig…
源码文件
/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that …
源码文件
-- megafunction wizard: %LPM_FF% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_ff -- ===========================…
源码文件
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity div_sheng is port( clk : in…
源码文件
L1_inst : L1 PORT MAP( result => result_sig );
源码文件
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity aclink3 is …
源码文件
/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that …
源码文件
library ieee; use ieee.std_logic_1164.all; entity mul3 is port(in1,in2,in3:std_logic_vector(7 downto 0); sela,selb,selc…