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assign

  • Insert table of contents: Create some pages, assign labels to them and insert a table of conten

    Insert table of contents: Create some pages, assign labels to them and insert a table of contents at the beginning of the document

    标签： table contents Insert Create

    上传时间： 2016-04-20

    上传用户：zuozuo1215

  • FPGA Verilog,双向端口的研究,比较全,由assign和ALWAYS模块组成,测试可用

    FPGA Verilog,双向端口的研究,比较全,由assign和ALWAYS模块组成,测试可用

    标签： Verilog assign ALWAYS FPGA

    上传时间： 2016-04-26

    上传用户：daoxiang126

  • 可视界面监狱管理系统 添加更改删除狱警囚犯 增加减少囚犯服刑年限 显示狱警工作年限 增加减少狱警工资 assign狱警囚犯到不同囚室

    可视界面监狱管理系统 添加更改删除狱警囚犯 增加减少囚犯服刑年限 显示狱警工作年限 增加减少狱警工资 assign狱警囚犯到不同囚室，等

    标签： assign 减 可视 删除

    上传时间： 2013-12-26

    上传用户：alan-ee

  • 同一基类型的两分辨类型的赋值相容问题,各个源描述的编译顺序是:logic.vhd,assign.vhd

    同一基类型的两分辨类型的赋值相容问题,各个源描述的编译顺序是:logic.vhd,assign.vhd

    标签： vhd assign logic 分辨

    上传时间： 2014-12-05

    上传用户：ghostparker

  • The combinatorial core of the OVSF code assignment problem that arises in UMTS is to assign some no

    The combinatorial core of the OVSF code assignment problem that arises in UMTS is to assign some nodes of a complete binary tree of height h (the code tree) to n simultaneous connections, such that no two assigned nodes (codes) are on the same root-to-leaf path. Each connection requires a code on a specified level. The code can change over time as long as it is still on the same level. We consider the one-step code assignment problem: Given an assignment, move the minimum number of codes to serve a new request. Minn and Siu proposed the so-called DCAalgorithm to solve the problem optimally. We show that DCA does not always return an optimal solution, and that the problem is NP-hard. We give an exact nO(h)-time algorithm, and a polynomial time greedy algorithm that achieves approximation ratio Θ(h). Finally, we consider the online code assignment problem for which we derive several results

    标签： combinatorial assignment problem arises

    上传时间： 2014-01-19

    上传用户：BIBI

  • Your application should never assign a seat that has already been assigned. When the economy sectio

    Your application should never assign a seat that has already been assigned. When the economy section is full, your application should ask the person if it is acceptable to be placed in the first-class section (and vice versa). If yes, make the appropriate seat assignment.

    标签： application assigned already economy

    上传时间： 2014-10-24

    上传用户：zhichenglu

  • FPGA Verilog

    FPGA Verilog,双向端口的研究,比较全,由assign和ALWAYS模块组成,测试可用

    标签： Verilog FPGA

    上传时间： 2013-08-22

    上传用户：longlong12345678

  • Hyperlynx仿真应用:阻抗匹配

    Hyperlynx仿真应用:阻抗匹配.下面以一个电路设计为例，简单介绍一下PCB仿真软件在设计中的使用。下面是一个DSP硬件电路部分元件位置关系(原理图和PCB使用PROTEL99SE设计)，其中DRAM作为DSP的扩展Memory(64位宽度，低8bit还经过3245接到FLASH和其它芯片)，DRAM时钟频率133M。因为频率较高，设计过程中我们需要考虑DRAM的数据、地址和控制线是否需加串阻。下面，我们以数据线D0仿真为例看是否需要加串阻。模型建立首先需要在元件公司网站下载各器件IBIS模型。然后打开Hyperlynx,新建LineSim File(线路仿真—主要用于PCB前仿真验证)新建好的线路仿真文件里可以看到一些虚线勾出的传输线、芯片脚、始端串阻和上下拉终端匹配电阻等。下面，我们开始导入主芯片DSP的数据线D0脚模型。左键点芯片管脚处的标志，出现未知管脚，然后再按下图的红线所示线路选取芯片IBIS模型中的对应管脚。 3http://bbs.elecfans.com/ 电子技术论坛 http://www.elecfans.com 电子发烧友点OK后退到“assign Models”界面。选管脚为“Output”类型。这样，一样管脚的配置就完成了。同样将DRAM的数据线对应管脚和3245的对应管脚IBIS模型加上(DSP输出，3245高阻，DRAM输入)。下面我们开始建立传输线模型。左键点DSP芯片脚相连的传输线，增添传输线，然后右键编辑属性。因为我们使用四层板，在表层走线，所以要选用“Microstrip”，然后点“Value”进行属性编辑。这里，我们要编辑一些PCB的属性，布线长度、宽度和层间距等，属性编辑界面如下：再将其它传输线也添加上。这就是没有加阻抗匹配的仿真模型(PCB最远直线间距1.4inch，对线长为1.7inch)。现在模型就建立好了。仿真及分析下面我们就要为各点加示波器探头了，按照下图红线所示路径为各测试点增加探头：为发现更多的信息，我们使用眼图观察。因为时钟是133M，数据单沿采样，数据翻转最高频率为66.7M，对应位宽为7.58ns。所以设置参数如下：之后按照芯片手册制作眼图模板。因为我们最关心的是接收端(DRAM)信号，所以模板也按照DRAM芯片HY57V283220手册的输入需求设计。芯片手册中要求输入高电平VIH高于2.0V，输入低电平VIL低于0.8V。DRAM芯片的一个NOTE里指出，芯片可以承受最高5.6V，最低-2.0V信号(不长于3ns)：按下边红线路径配置眼图模板：低8位数据线没有串阻可以满足设计要求，而其他的56位都是一对一，经过仿真没有串阻也能通过。于是数据线不加串阻可以满足设计要求，但有一点需注意，就是写数据时因为存在回冲，DRAM接收高电平在位中间会回冲到2V。因此会导致电平判决裕量较小，抗干扰能力差一些，如果调试过程中发现写RAM会出错，还需要改版加串阻。

    标签： Hyperlynx 仿真 阻抗匹配

    上传时间： 2013-11-05

    上传用户：dudu121

  • 6小时学会labview

    6小时学会labview, labview Six Hour Course – Instructor Notes   This zip file contains material designed to give students a working knowledge of labview in a 6 hour timeframe. The contents are: Instructor Notes.doc – this document. labviewIntroduction-SixHour.ppt – a PowerPoint presentation containing screenshots and notes on the topics covered by the course. Convert C to F (Ex1).vi – Exercise 1 solution VI. Convert C to F (Ex2).vi – Exercise 2 solution subVI. Thermometer-DAQ (Ex2).vi – Exercise 2 solution VI. Temperature Monitor (Ex3).vi – Exercise 3 solution VI. Thermometer (Ex4).vi – Exercise 4 solution subVI. Convert C to F (Ex4).vi – Exercise 4 solution subVI. Temperature Logger (Ex4).vi – Exercise 4 solution VI. Multiplot Graph (Ex5).vi – Exercise 5 solution VI. Square Root (Ex6).vi – Exercise 6 solution VI. State Machine 1 (Ex7).vi – Exercise 7 solution VI.   The slides can be presented in two three hour labs, or six one hour lectures. Depending on the time and resources available in class, you can choose whether to assign the exercises as homework or to be done in class. If you decide to assign the exercises in class, it is best to assign them in order with the presentation. This way the students can create VI’s while the relevant information is still fresh. The notes associated with the exercise slide should be sufficient to guide the students to a solution. The solution files included are one possible solution, but by no means the only solution.

    标签： labview

    上传时间： 2013-10-12

    上传用户：zjwangyichao

  • Foundation入门—仿真

    Explain how to open the Waveform Viewer for Verification ? State how to insert nodes into the Waveform Viewer ? Tell how to assign Stimulus with the Stimulator Selector

    标签： Foundation 仿真

    上传时间： 2013-11-04

    上传用户：gps6888

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