I2C总线高频头控制程序(Keil C51程序 基于芯片TSA5522系列) /*I2C总线高频头控制Keil C51程序(PLL芯片为TSA5522系列) *///--------------------------------------------------------------------------//// 源程序大公开 //// (c) Copyright 2001－2003 xuwenjun //// All Rights Reserved //// V1.00 ////--------------------------------------------------------------------------////标 题: I2C总线高频头控制程序(PLL芯片为TSA5522系列) ////文件名: xwj_fi1256.c ////版 本: V1.00 ////修改人: 徐文军 E-mail:xuwenjun@21cn.com ////日 期: 06-02-26 首次公开 ////描 述: I2C总线高频头控制程序(PLL芯片为TSA5522系列) ////声 明: //// 以下代码仅免费提供给学习用途，但引用或修改后必须在文件中声明出处. //// 如用于商业用途请与作者联系. E-mail:xuwenjun@21cn.com //// 有问题请mailto xuwenjun@21cn.com 欢迎与我交流! ////--------------------------------------------------------------------------////老版本: 无 老版本文件名: ////创建人: 徐文军 E-mail:xuwenjun@21cn.com ////日 期: 06-02-26 ////描 述: ////--------------------------------------------------------------------------// /* 频率单位为KHz */#define FUENCY 38900 /* 中频频率 */#define PLLdataH(f) ((f+FUENCY)*16/1000/256) /* 频率数据高 第1字节*/#define PLLdataL(f) ((f+FUENCY)*16/1000%256) /* 频率数据低 第2字节*/#define PLLCON1 0x8e /* 控制字1 第3字节*/ /* 控制字2 第4字节*/#define PLLCON2(f) (((f)<(168000))?(0xa0):(((f)<(450000))?(0x90):(0x30)))#define PLLdata3(fchan) PLLdataH (fchan),PLLdataL (fchan),PLLCON2 (fchan)
上传时间： 2013-11-10
上传用户：nanfeicui
This overview guide describes all the peripherals available for TMS320x28xx and TMS320x28xxx devices.Section 2 shows the peripherals used by each device. Section 3 provides descriptions of the peripherals.You can download the peripheral guide by clicking on the literature number, which is linked to the portable document format (pdf) file.
上传时间： 2013-11-21
上传用户：HGH77P99
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their productsor to discontinue any product or service without notice, and advise customers to obtain the latestversion of relevant information to verify, before placing orders, that information being relied onis current and complete. All products are sold subject to the terms and conditions of sale suppliedat the time of order acknowledgement, including those pertaining to warranty, patentinfringement, and limitation of liability
上传时间： 2013-12-26
上传用户：凌云御清风
Xilinx UltraScale™ 架构针对要求最严苛的应用，提供了前所未有的ASIC级的系统级集成和容量。 UltraScale架构是业界首次在All Programmable架构中应用最先进的ASIC架构优化。该架构能从20nm平面FET结构扩展至16nm鳍式FET晶体管技术甚至更高的技术，同 时还能从单芯片扩展到3D IC。借助Xilinx Vivado®设计套件的分析型协同优化，UltraScale架构可以提供海量数据的路由功能，同时还能智能地解决先进工艺节点上的头号系统性能瓶颈。 这种协同设计可以在不降低性能的前提下达到实现超过90%的利用率。 UltraScale架构的突破包括： • 几乎可以在晶片的任何位置战略性地布置类似于ASIC的系统时钟，从而将时钟歪斜降低达50% • 系统架构中有大量并行总线，无需再使用会造成时延的流水线，从而可提高系统速度和容量 • 甚至在要求资源利用率达到90%及以上的系统中，也能消除潜在的时序收敛问题和互连瓶颈 • 可凭借3D IC集成能力构建更大型器件，并在工艺技术方面领先当前行业标准整整一代 • 能在更低的系统功耗预算范围内显著提高系统性能，包括多Gb串行收发器、I/O以及存储器带宽 • 显著增强DSP与包处理性能 赛灵思UltraScale架构为超大容量解决方案设计人员开启了一个全新的领域。
标签： UltraScale Xilinx 架构
上传时间： 2013-11-17
上传用户：皇族传媒
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-14
上传用户：fdmpy
ZBT SRAM控制器参考设计,xilinx提供VHDL代码 Description: Contains the following files readme.txt appnote_zbtp.vhd appnote_zbtf.vhd appnote_zbt.ucf Platform: All Installation/Use: Use 'unzip' on the .zip file and 'gunzip' followed by 'tar -xvf' on the .tar.gz file.
上传时间： 2013-11-24
上传用户：31633073
ref-sdr-sdram-vhdl代码 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.
上传时间： 2013-11-13
上传用户：takako_yang
There is no doubt that remote controls are extremely popular and it has become very hard to imagine a world without them. They are used to control all manner of house appliances like the TV set, the stereo, the VCR, and the satellite receiver.
上传时间： 2013-11-13
上传用户：顶得柱
The field of microelectromechanical systems (MEMS), particularly micromachinedmechanical transducers, has been expanding over recent years, and the productioncosts of these devices continue to fall. Using materials, fabrication processes, anddesign tools originally developed for the microelectronic circuits industry, newtypes of microengineered device are evolving all the time—many offering numerousadvantages over their traditional counterparts. The electrical properties of siliconhave been well understood for many years, but it is the mechanical properties thathave been exploited in many examples of MEMS. This book may seem slightlyunusual in that it has four editors. However, since we all work together in this fieldwithin the School of Electronics and Computer Science at the University of Southampton,it seemed natural to work together on a project like this. MEMS are nowappearing as part of the syllabus for both undergraduate and postgraduate coursesat many universities, and we hope that this book will complement the teaching thatis taking place in this area.
上传时间： 2013-10-16
上传用户：朗朗乾坤
