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IEEE 802.16a RS-CC编译码VLSI算法研究及FPGA实现
本论文依据IEEE802.16a物理层对RS-CC码的参数要求，研究了RS-CC码的高速编、译码的VLSI硬件算法，同时对FPGA开发技术进行了研究，以VerilogHDL为描述语言，在Xilin...
VLSI Design
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DESIGN PATTERNS JAVA COMPANION Design patterns began to be recognized more formally in the early 1
DESIGN PATTERNS JAVA COMPANION Design patterns began to be recognized more formally in the early 1...
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-- Title : Barrel Shifter (Pure combinational) -- This VHDL design file is an open design you can r
-- Title : Barrel Shifter (Pure combinational) -- This VHDL design file is an open design you can r...
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introduced the filter design process in TI s DSP, Include some real example for filter design
introduced the filter design process in TI s DSP, Include some real example for filter design...
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FIR Filter Design This chapter treats the design of linear-phase FIR filters. The assignments are
FIR Filter Design This chapter treats the design of linear-phase FIR filters. The assignments are ...
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SOME BACKGROUND ON DESIGN PATTERNS The term “design patterns” sounds a bit formal to the uninitiate
SOME BACKGROUND ON DESIGN PATTERNS The term “design patterns” sounds a bit formal to the uninitiate...
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The DSP Design Flow workshop provides
The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and i...
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DESCRIPTION: DDS design BY PLD DEVICES
* DESCRIPTION: DDS design BY PLD DEVICES.\r\n *\r\n * AUTHOR: Sun Yu\r\n *\r\n * HISTORY: 12/06/2002...
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Design Safe Verilog State Machine（Synplicity）
One of the strengths of Synplify is the Finite State Machine compiler. This is a powerful...