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SystemVerilog for Design
·SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Langua...
VLSI Design
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XILINX ISE DESIGN SUITE 14.7
Xilinx ISE Design Suite是利用新技术来降低总设计成本的电子设计套件软件，并且实现了比任何其它 PLD 解决方案更高的性能。...
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Good Code Document,this is a C++ design help document,is good ,help design program
Good Code Document,this is a C++ design help document,is good ,help design program...
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DBDesigner 4 is a database design system that integrates database design, modelling, creation and ma
DBDesigner 4 is a database design system that integrates database design, modelling, creation and ma...
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Design of Integrated Circuits for Optical Communications deals with the design of high-speed integra
Design of Integrated Circuits for Optical Communications deals with the design of high-speed integra...
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Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design docu
Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design docu...
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IEEE 802.16a RS-CC编译码VLSI算法研究及FPGA实现
本论文依据IEEE802.16a物理层对RS-CC码的参数要求，研究了RS-CC码的高速编、译码的VLSI硬件算法，同时对FPGA开发技术进行了研究，以VerilogHDL为描述语言，在Xilin...
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基于AVS-P7标准插值计算模块的VLSI实现
· 摘要： AVS-P7(即AVS-M)是AVS系列标准中的第七部分移动视频编码标准.提出一种基于AVS-P7运动补偿单元的VLSI结构,采用改进的片上RAM读写机制和插值计算单...
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VLSi KL partitioning Algorithm based programme for 100 nodes. It s dynamic progremme so by changing
VLSi KL partitioning Algorithm based programme for 100 nodes. It s dynamic progremme so by changing...