一种基于FPGA的Viterbi译码器一种基于FPGA的Viterbi译码器
一种基于FPGA的Viterbi译码器一种基于FPGA的Viterbi译码器...
VITERBI技术资料
📦 资源总数：185
💻 源代码：1266
📚 VITERBI全部资料 (185个)
it is a matlab program that describes DVB-S channel and simulation of Viterbi decoding
it is a matlab program that describes DVB-S channel and simulation of Viterbi decoding...
The Viterbi algorithm
The Viterbi algorithm...
viterbi algorithm_code_verilog
viterbi algorithm_code_verilog...
Hard Viterbi QPSK in AWGN, Rayleight soft Viterbi QAM in AWGN, Rayleight viterbi QAM in AWGN, Rayl
Hard Viterbi QPSK in AWGN, Rayleight soft Viterbi QAM in AWGN, Rayleight viterbi QAM in AWGN, Rayl...
Viterbi in java. ViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterb
Viterbi in java. ViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterb...
FPGA-based Viterbi convolutional coding and decoding of the Research and Implementation
FPGA-based Viterbi convolutional coding and decoding of the Research and Implementation...
It is turbo encoder and decoder qritten for communication module has viterbi
It is turbo encoder and decoder qritten for communication module has viterbi...
基于FPGA的viterbi设计及Verilog代码
viterbi译码算法是一种卷积码的解码算法。优点不说了。缺点就是随着约束长度的增加算法的复杂度增加很快。约束长度N为7时要比较的路径就有64条，为8时路径变为128条。 (2<<(N-1...
Verilog源代码关于viterbi设计
(n, k, N)卷积码的状态数为2k (N−1) ，对每一时刻要 做2k (N−1) 次“加－比－存”操作，每一操作包括2k 次加法和2k −1 次比较，同时要保留2k (N−...