VERILOG
VerilogHDL是一种硬件描述语言，以文本形式来描述数字系统硬件的结构和行为的语言，用它可以表示逻辑电路图、逻辑表达式，还可以表示数字逻辑系统所完成的逻辑功能。VerilogHDL和VHDL是世界上最流行的两种硬件描述语言，都是在20世纪80年代中期开发出来的。前者由GatewayDesignA...
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VERILOG 热门资料
查看全部 500 份 →(2003 prentice-hall)verilog hdl：a guide to digital design and synthesis(2nd edition).rar
(2003 prentice-hall)verilog hdl：a guide to digital design and synthesis(2nd edition).rar
2014-01-17
54
this a book about the verilog-hdl design and circuit simulation and synthesize example
this a book about the verilog-hdl design and circuit simulation and synthesize example
2016-11-03
54
This Verilog HDL description implements a UART Version 1.1 : Original Creation 2.1 : added commen
This Verilog HDL description implements a UART Version 1.1 : Original Creation 2.1 : added comments
2016-05-27
81
verilog code which receive from uart RX and then output to lcd text display.
verilog code which receive from uart RX and then output to lcd text display.
2016-03-07
122
采用Verilog HDL语言编写的数字频率计
采用Verilog HDL语言编写的数字频率计，被测波形分别为方波、三角波和正弦波；采用6个数码管显示结果，三档量程可调，工程价值很高，
2016-03-21
106