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John.Wiley.&.Sons_1997_Simulation.Techniques..Models.of.Communication.Signals.and.Processes通信仿真的好书

John.Wiley.&.Sons_1997_Simulation.Techniques..Models.of.Communication.Signals.and.Processes通信仿真的好书

标签： Communication Simulation Techniques Processes

上传时间： 2015-07-03

上传用户：gtf1207
DVB DOCUMENT A025 Guideline for Implementation and Use of the Common Interface for DVB Decoder App

DVB DOCUMENT A025 Guideline for Implementation and Use of the Common Interface for DVB Decoder Applications

标签： Implementation DVB Guideline for

上传时间： 2015-07-03

上传用户：xsnjzljj
The J2000 codec was written in an effort to produce the cleanest and simplest implementation possibl

The J2000 codec was written in an effort to produce the cleanest and simplest implementation possible of the JPEG-2000 standard. We have put a particular emphasis on good architecture design and code simplicity, while at the same time providing an implementation as complete and efficient as possible. The source code for the codec is freely available for anyone to study or even for use in commercial programs. We hope that our open development process and our focus on clean, straightforward code will help make the J2000 codec become a reference implementation of the JPEG-2000 standard

标签： implementation cleanest simplest produce

上传时间： 2015-07-03

上传用户：dengzb84
TrainReset:there are many trains need to drive out of the station .In terms of their numbers from sm

TrainReset:there are many trains need to drive out of the station .In terms of their numbers from small to large.There are only three railways used to place the trains ,and also need the same order.

标签： TrainReset numbers station trains

上传时间： 2015-07-04

上传用户：moerwang
the verilog model of sdram-mt48lc2m32b2 device.

the verilog model of sdram-mt48lc2m32b2 device.

标签： sdram-mt verilog device model

上传时间： 2014-08-20

上传用户：AbuGe
the verilog model of sram IS61LV25616AL device.

the verilog model of sram IS61LV25616AL device.

标签： verilog device model 25616

上传时间： 2014-01-21

上传用户：huannan88
the verilog model of async_fifo.

the verilog model of async_fifo.

标签： async_fifo verilog model the

上传时间： 2014-07-03

上传用户：heart520beat
the model of cpu ARM7TDMI.

the model of cpu ARM7TDMI.

标签： model TDMI the cpu

上传时间： 2015-07-04

上传用户：ommshaggar
the vhdl model of usb. it is very helpful.

the vhdl model of usb. it is very helpful.

标签： helpful model vhdl very

上传时间： 2014-01-21

上传用户：zhyiroy
一种基于二维链表的稀疏矩阵模半板类设计 A template Class of sparse matrix. Key technology: bin,2-m linked matrix. con

一种基于二维链表的稀疏矩阵模半板类设计 A template Class of sparse matrix. Key technology: bin,2-m linked matrix. constructors: 1.normal constuctor 2.copy constuctor. 3.assignment constructor. Basic operator: 1. addition(sub) of two matrix 2. inverse of a matrix. 3. multiply of two matrix. etc.

标签： matrix technology template linked

上传时间： 2013-12-13

上传用户：lwwhust