Log Shifter Gate Level Design using Verilog(IC design Lab) and Lab Note
标签： Lab Shifter Verilog Design
上传时间： 2016-12-01
上传用户：cylnpy
时间片系统time slicing system ，基于PICDEM 2 PLUS开发板pic16f877a芯片上的代码。
上传时间： 2016-12-01
上传用户：zhaiyanzhong
The ISD51_Demo project for the MSC1200 shows how to use the ISD51 In-System-Debugger with flash breakpoints or hardware breakpoints. By default, it is configured for flash breakpoints which allow you to set real-time breakpoints in your software. Using Flash breakpoints has also the benefit that no special handing for the shared interrupt vector is required, since the hardware break registers of the MSC1200 are not used at all.
标签： In-System-Debugger ISD the project
上传时间： 2014-11-18
上传用户：dongqiangqiang
About communication in Vxworks system
标签： communication Vxworks system About
上传时间： 2014-01-07
上传用户：waitingfy
ADPLL of high level phase locked loop
上传时间： 2016-12-04
上传用户：wpwpwlxwlx
图书馆管理系统 library control system
标签： library control system 图书馆
上传时间： 2014-08-24
上传用户：wff
monitor the local system resource
标签： resource monitor system local
上传时间： 2016-12-06
上传用户：xieguodong1234
embeded operation system
上传时间： 2016-12-06
上传用户：ippler8
The System Management BIOS Reference Specification addresses how motherboard and system vendors present management information about their products in a standard format by extending the BIOS interface on Intel architecture systems. The information is intended to allow generic instrumentation to deliver this data to management applications that use CIM (the WBEM data model) or direct access and eliminates the need for error prone operations like probing system hardware for presence detection.
标签： Specification motherboard Management Reference
上传时间： 2013-12-10
上传用户：凤临西北
SoC-Wishbone System IP核的VHDL语言源代码
标签： SoC-Wishbone System VHDL IP核
上传时间： 2016-12-08
上传用户：13188549192
