Synthesis+Tool 源代码

汇集 Synthesis+Tool 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。

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源码文件

/* * progctrl_rom generated by KCAsm at Sat May 26 15:39:08 EDT 2007 */ module progctrl_rom(address, instruction, clk); input […

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module uclock (address, instruction, clk); input [9:0] address; input clk; output [17:0] instruction; RAMB16_S18 ram_1024_x_18…

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module testint_rom(address, instruction, clk); input [9:0] address; output [17:0] instruction; input clk; RAMB16_S18 ram_1024_x_18…

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module pb3m_test_rom(address, instruction, clk); input [9:0] address; output [17:0] instruction; input clk; RAMB16_S18 ram_1024_x_…

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module testsub_rom(address, instruction, clk); input [9:0] address; output [17:0] instruction; input clk; RAMB16_S18 ram_1024_x_18…

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module pb3_ret_rom(address, instruction, clk); input [9:0] address; output [17:0] instruction; input clk; RAMB16_S18 ram_1024_x_18…

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module int_test2_rom(address, instruction, clk); input [9:0] address; output [17:0] instruction; input clk; RAMB16_S18 ram_1024_x_…

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module pb3_int_rom(address, instruction, clk); input [9:0] address; output [17:0] instruction; input clk; RAMB16_S18 ram_1024_x_18…

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module test3_rom(address, instruction, clk); input [9:0] address; output [17:0] instruction; input clk; RAMB16_S18 ram_1024_x_18( …

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module pb3_test_rom(address, instruction, clk); input [9:0] address; output [17:0] instruction; input clk; RAMB16_S18 ram_1024_x_1…