源码文件
library IEEE; use IEEE.std_logic_1164.all; use work.primitive.all; entity bidirbuffer is port ( input: in std_logic; …
Structural+Hazard 源代码
汇集 Structural+Hazard 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
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源码文件
library IEEE; use IEEE.std_logic_1164.all; use work.primitive.all; entity tribuffer is port ( input: in std_logic; en…
源码文件
library IEEE; use IEEE.std_logic_1164.all; use work.primitive.all; entity FEWGATES is port ( a,b,c,d: in std_logic; y…
源码文件
library IEEE; use IEEE.std_logic_1164.all; use work.primitive.all; entity LogicFcn is port ( A: in std_logic; B: in std…
源码文件
-- A Variety of Adder Styles -- download from: www.fpga.com.cn & www.pld.com.cn ------------------------------------------------…
源码文件
module AND(in1, in2, out); //Structural model of AND gate from two NANDS input in1, in2; output out; wire w1; // two ins…
源码文件
-- A Variety of Adder Styles -- download from: www.fpga.com.cn & www.pld.com.cn ------------------------------------------------…
源码文件
------------------------------------------------------------------------ -- Single-bit adder -----------------------------------…
源码文件
LIBRARY IEEE; USE IEEE.Std_Logic_1164.ALL; USE IEEE.Std_Logic_Unsigned.ALL; ENTITY example IS END; ARCHITECTURE structural OF …
源码文件
LIBRARY IEEE; USE IEEE.Std_Logic_1164.ALL; ENTITY half_adder IS GENERIC(tpd : TIME := 10 ns); PORT(in1, in2: IN Std_Logic;…