源码文件
#-- Synplicity, Inc. #-- Version 7.7.1 #-- Project file E:\QProj\AdderE\AdderE.prd #-- Written on Mon May 01 16:07:01 2006…
SYNPLICITY 源代码
Synplicity，专注于FPGA设计与验证的领先工具，为电子工程师提供高效、精确的设计解决方案。通过先进的逻辑综合与优化技术，显著提升硬件性能并缩短开发周期。广泛应用于通信、消费电子及航空航天等领域。掌握Synplicity不仅能够增强您的专业技能，还能加速项目从概念到实现的…
收录资源 220 份
全站深度检索
共匹配 220 份工程资源
· 第 7 / 22 页
源码文件
source "D:/Synplicity/Synplify_771/lib/altera/quartus_cons.tcl" syn_create_and_open_prj AdderE syn_create_and_open_csf AdderE s…
源码文件
# # # # Created by Synplify VHDL Compiler version Compilers 2.8.1, Build 050R from Synplicity, Inc. # Copyright 1994-2004 Synp…
源码文件
# # Synplicity Verification Interface File # Generated using Synplify-pro # # Copyright (c) 1996-2004 Synplicity, Inc. # All …
源码文件
#-- Synplicity, Inc. #-- Version Synplify Pro 8.1 #-- Project file G:\taoyuhui\synplifywork_new\statemachine11.2\statemachine112…
源码文件
# # Synplicity Verification Interface File # Generated using Synplify-pro # # Copyright (c) 1996-2005 Synplicity, Inc. # All …
源码文件
# # Synplicity Verification Interface File # Generated using Synplify-pro # # Copyright (c) 1996-2005 Synplicity, Inc. # All …
源码文件
#-- Synplicity, Inc. #-- Version Synplify Pro 8.1 #-- Project file G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult.prd #…
源码文件
#-- Synplicity, Inc. #-- Version Synplify Pro 8.1 #-- Project file G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.prd …
源码文件
#-- Synplicity, Inc. #-- Version 7.0.2 #-- Project file \\Judd_ql_dallas\D\mips\ahb\interface_ex\verilog\demo_amba.prd #-- W…