st_mult1.vif

veilog实现的状态机乘法器.可以参考

#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#

# Set logfile options
vif_set_result_file  st_mult1.vlf

# Set technology for TCL script
vif_set_technology -architecture FPGA -vendor Altera

# RTL and technology files
vif_add_library -original $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
vif_add_file -original -verilog ../st_mult1.v
vif_set_top_module -original -top st_mult1
 
vif_add_library -translated $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
vif_add_file -translated -verilog st_mult1.vqm
vif_set_top_module -translated -top st_mult1